Hitachi SH7032 - Timer Control Register (TCR)

242
10.2.9 Timer Control Register (TCR)
The ITU has five 8-bit timer control registers (TCR), one for each channel.
TCR is an 8-bit read/write register that selects the timer counter clock, the edges of the external
clock source, and the counter clear source. TCR is initialized to H'80 or H'00 by a reset and in
standby mode.
Table 10.7 Timer Control Register (TCR)
Channel
Abbrevi-
ation Function
0 TCR0
1 TCR1
2 TCR2
3 TCR3
4 TCR4
Bit: 7 6 5 4 3 2 1 0
Bit name: — CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0
Initial value: * 0000000
R/W: — R/W R/W R/W R/W R/W R/W R/W
Note: *Undefined
• Bit 7 (Reserved): Bit 7 is read as undefined. The write value should be 0 or 1.
TCR controls the TCNTs. The TCRs have the same functions on all channels.
When channel 2 is set for phase counting mode, setting the CKEG1, CKEG2,
and TPSC2–TPSC0 bits will have no effect.