243
• Bits 6 and 5 (Counter Clear 1 and 0 (CCLR1 and CCLR0)): CCLR1 and CCLR0 select the
counter clear source.
Bit 6:
CCLR1
Bit 5:
CCLR0 Description
0 0 TCNT is not cleared (Initial value)
1 TCNT is cleared by general register A (GRA) compare match or input
capture
*
1
1 0 TCNT is cleared by general register B (GRB) compare match or input
capture
*
1
1 Synchronizing clear: TCNT is cleared in synchronization with clear of other
timer counters operating in sync
*
2
Notes: *1 When GR is functioning as an output compare register, TCNT is cleared upon a
compare match. When functioning as an input capture register, TCNT is cleared upon
input capture.
*2 The timer synchro register (TSNC) sets the synchronization.
• Bits 4 and 3 (External Clock Edge 1/0 (CKEG1 and CKEG0)): CKEG1 and CKEG0 select
external clock input edge. When channel 2 is set for phase counting mode, settings of the
CKEG1 and CKEG0 bits in TCR are ignored and the phase counting mode operation takes
priority.
Bit 4:
CKEG1
Bit 3:
CKEG0 Description
0 0 Count rising edges (Initial value)
1 Count falling edges
1 — Count both rising and falling edges
• Bits 2–0 (Timer Prescaler 2–0 (TPS2–TPS0)): TPS2–TPS0 select the counter clock source.
When TPSC2 = 0 and an internal clock source is selected, the timer counts only falling edges.
When TPSC2 = 1 and an external clock is selected, the count edge is as set by CKEG1 and
CKEG0. When phase counting mode is selected for channel 2 (the MDF bit in the timer mode
register is 1), the settings of TPSC2–TPSC0 in TCR2 are ignored and the phase counting
operation takes priority.
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