Hitachi SH7032 - Page 28

vii
11.1.2 Block Diagram...................................................................................................... 310
11.1.3 Input/Output Pins.................................................................................................. 311
11.1.4 Registers................................................................................................................312
11.2 Register Descriptions.......................................................................................................... 313
11.2.1 Port B Control Registers 1 and 2 (PBCR1, PCBR2) ............................................ 313
11.2.2 Port B Data Register (PBDR)................................................................................ 314
11.2.3 Next Data Register A (NDRA) ............................................................................. 314
11.2.4 Next Data Register B (NDRB).............................................................................. 316
11.2.5 Next Data Enable Register A (NDERA)............................................................... 318
11.2.6 Next Data Enable Register B (NDERB) ............................................................... 318
11.2.7 TPC Output Control Register (TPCR).................................................................. 319
11.2.8 TPC Output Mode Register (TPMR).................................................................... 321
11.3 Operation............................................................................................................................ 322
11.3.1 Overview............................................................................................................... 322
11.3.2 Output Timing....................................................................................................... 323
11.3.3 Examples of Use of Ordinary TPC Output ........................................................... 324
11.3.4 TPC Output Non-Overlap Operation.................................................................... 327
11.3.5 TPC Output by Input Capture ............................................................................... 331
11.4 Usage Notes........................................................................................................................ 332
11.4.1 Non-Overlap Operation......................................................................................... 332
Section 12 Watchdog Timer (WDT)............................................................................... 335
12.1 Overview ............................................................................................................................ 335
12.1.1 Features ................................................................................................................. 335
12.1.2 Block Diagram...................................................................................................... 336
12.1.3 Pin Configuration.................................................................................................. 336
12.1.4 Register Configuration.......................................................................................... 337
12.2 Register Descriptions.......................................................................................................... 337
12.2.1 Timer Counter (TCNT)......................................................................................... 337
12.2.2 Timer Control/Status Register (TCSR)................................................................. 338
12.2.3 Reset Control/Status Register (RSTCSR)............................................................. 339
12.2.4 Notes on Register Access...................................................................................... 340
12.3 Operation............................................................................................................................ 342
12.3.1 Operation in Watchdog Timer Mode.................................................................... 342
12.3.2 Operation in Interval Timer Mode........................................................................ 344
12.3.3 Operation in Standby Mode.................................................................................. 344
12.3.4 Timing of Overflow Flag (OVF) Setting.............................................................. 345
12.3.5 Timing of Watchdog Timer Overflow Flag (WOVF) Setting.............................. 345
12.4 Usage Notes........................................................................................................................ 346
12.4.1 TCNT Write and Increment Contention................................................................ 346
12.4.2 Changing CKS2–CKS0 Bit Values....................................................................... 346
12.4.3 Changing Watchdog Timer/Interval Timer Modes............................................... 346
12.4.4 System Reset With WDTOVF.............................................................................. 347