Hitachi SH7032 - Page 516

481
T
1
T
2
t
AD
t
RDD
t
CSD2
t
RSD
t
RDAC2
*
1
t
ACC2
*
2
t
RDS
t
RDH
*
3
t
DACD2
t
DACD1
t
WSD2
t
WSD1
t
DACD3
t
DACD3
t
WDH
t
WDD1
t
WPDH
t
WPDD1
CK
A21–A0
HBS, LBS
CSn
DACK0
DACK1
(Read)
RD (Read)
WRH, WRL,
WR (Write)
AD15–AD0
DPH, DPL
(Read)
AD15–AD0
(Write)
DPH, DPL
(Write)
DACK0
DACK1
(Write)
t
CSD1
Notes: *1 For t
RDAC2
, use t
cyc
× (n + 1.65) – 20 (for 35% duty) or t
cyc
× (n + 1.5) – 20 (for
50% duty) instead of t
cyc
× (n + 2) – t
RDD
– t
RDS
.
*2 For t
ACC2
, use t
cyc
× (n + 2) – 30 instead of t
cyc
× (n + 2) – t
AD
(or t
CSD1
) – t
RDH
.
*3t
RDH
is measured from A21–A0, CSn, or RD, whichever is negated first.
Figure 20.9 Basic Bus Cycle: Two-State Access