Hitachi SH7032 - Page 536

501
CK
A21–A0
RAS
CAS
WRH, WRL
,
WR
(Write)
DACK0
DACK1
(Write)
AD15–AD0
DPH, DPL
(Write)
DPH, DPL
(Write)
t
AD
T
p
T
r
T
c
Silent
cycle
T
c
t
AD
t
RASD1
t
RASD2
t
ASC
t
DACD4
t
DACD5
t
DACD5
Row address Column address Column address
RD (Write)
t
WSD4
t
WSD3
t
WDD2
t
WDH
t
WPDD2 t
WPDH
Figure 20.25 (b) DRAM Bus Cycle (Short-Pitch, High-Speed Page Mode: Write)
Note: For details of the silent cycle, see section 8.5.5, DRAM Burst Mode.