HP 4284A - Page 222

Table 7-4. Status Byte Assignments
Bit No. Bit Weight Description
7 128 Operation Status Event Register Summary Bit
This bit is set to \1" when one or more enabled bits of the op eration
status event register (discussed later in this chapter) has b een set to
\1". This bit is cleared when all bits of the op eration status register
are set to 0. (This bit isn't cleared by serial-p olling.)
6 64 Bit 6 serves two functions RQS/MSS depending on how it is read.
 RQS (Request Service) Bit
If bit 6 is read in the serial p olling pro cess, it is treated as the RQS
bit and is reset during the serial p olling pro cess.
 MSS (Master Summary) Bit
If bit 6 is read using the *STB? (status byte) query, it is treated as the
MSS bit, and its value is not changed by the executing the *STB?
query.
To understand this op eration think of the R
QS and MSS bits as two
inputs to a multiplexer ( mux ) and the output of the MUX b eing bit 6
of the status byte register.
During the serial p olling op eration the MUX path selected is from the
service request generation circuit to bit 6, so bit 6 represen
ts the RQS
bit.
During execution of the *STB? query the MUX path selected is from
the master summary bit generation circuit to bit 6, so bit 6 represen
ts
the MSS bit.
To clear the MSS bit, all bits of the original registers corresp onding to
the enabled summary bit in the status byte and the output buer of
the HP 4284A must b e cleared. When you read the status byte
including the MSS bit instead of the RQS bit, the *STB? query must
be used. *STB? query clears neither the MSS bit nor the RQS bit.
5 32 Standard Event Status Register Summary Bit
This bit is set to \1" when any enabled bits of the standard event
status register (discussed later in this section) has b een set to \1".
This bit is cleared when all bits of the standard ev
ent status register
are set to 0. (This bit isn't cleared b
y serial-p olling.)
4 16 MAV (Message Available) Bit
This bit is set to \1" whenever the HP 4284A has data available to
output. This bit is cleared when the available data is read.
(This bit isn't cleared by serial-p olling.)
3 8 always 0 (zero)
2 4 always 0 (zero)
1 2 always 0 (zero)
0 1 always 0 (zero)
Remote Control 7-21