Standard Event
Status Register
The standard event status register contains the 16-bits of the
operation status report which is dened in IEEE 488.2-1987 as
shown in Figure 7-19. If one or more enable bits of the standard
event status register is set to \1", bit 5 (standard event status
register summary bit) of the status byte is set to \1". Each bit of the
standard event status register is shown on the next page.
When each error bit (bit 2, bit 3, bit 4, and bit 5) of the standard
event status register is set to \1", an error message with the following
error numbers is input to the error queue. For details, refer to
Appendix B.
Bit No. Error No.
5 (Command Error)
0
100 to
0
178
4 (Execution Error)
0
211 to
0
230
3 (Device Sp ecic Error) 10 to 101,
0
310,
0
311
2 (Query Error)
0
400 to
0
440
When you read the contents of the standard event status register
using the
*ESR?
command, the standard event status register is
cleared, and bit 5 of the status byte is set to \0".
Remote Control 7-27
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