HP Series 37 - Page 95

Test Descriptions
Test
5. IRQ LOGIC -- Tests the interrupt logic on the SIB. First, the external interrupts are turned
off. An SMSK command is issued, disabling the TIC, and then an illegal address command is
issued. The illegal
command should generate an error (but not an interrupt, since the mask is
disabled).
The mask bit is checked by performing an RIOA of the channel with an RMSK
command. This results
in the hardware mask being returned and not the memory image. An
IPOLL is then issued to verify that the IRQ line is not set. The interrupt mask is now set to
enable the TIC. The process is repeated, and the IRQ is checked to verify that it is set.
Test 6. MEMORY -- Tests the SIB memory by running a checkerboard test (writing to each register of
each port with the Memory Diagnostic bit set and then cleared) and an address test. The SIB
memory is used as the DMA registers for the I/O ports.
Test 7. SEQUENCING -- Single-steps the L-Bus State Machine and then checks the state after each
cycle. An
error message is output if the test fails.
Test
8. TIMEOUT -- Tests the L-Bus timeout logic, which terminates the wait for either BusEnd
from the L-Bu8, or HALT from the DMA state machine. The timeout occurs when the L-Bus
handshake does not finish in the required time limit.
Test
9. BOARD ENABLE -- Tests the board enable logic that is on the SIB section of the TIC. This
logic includes
the board enable register and the L-Bus State Machine. The tests are as follows:
I) An INIT command is issued to clear the board.
2) The Diagnostic Control Register is set up to single-step and turn LOOPEN off.
3) Single-steps the board and checks that the FPLA (L-Bus State Machine) cycles between
States
0 and 4.
4) Enables the board by writing to Register 8, the Board Enable Register.
5) Single-steps to make certain that the L-Bus State Machine goes to State I after State 4
6) Turns on LOOPEN and completes the L-Bus Cycle.
Test
10. PORT POINTER -- Tests the Port Pointer logic. This is done as follows:
I) An INIT command is issued to clear the board.
2) Sets up the Diagnostic Control Register for single-stepping and LOOPEN off.
3) Sets up an illegal port pointer in the ':'ort Pointer Register (8).
4) Single-steps the L-Bus State Machine and checks that BUSGO is not asserted.
5) Waits an appropriate amount of time and checks that a timeout has occurred. The L-Bu8
State Machine waits for the handshake in reply to the BUSGO.
Te~t 1 1 FREEZE -- Tests the actions of the freeze bit of Regi~ter I.A (the Djagn()stj,~ C"ntrol
Rei"i~t"r) Thi~ hit c:,ll<e' the 1 -1'\,,' "'3t" \.,f,l'h;ne t" ,-v,lp h""vo>pn .t~te. n ,,,,1 <l ~,.,d ':''1<0<
the PCCs to halt.
Test
! 2. TIC Bt:S BUFFERS -- Tests the L-Bus buffers It uses D\1A test code to write data to) the
L-Bus and read the koped back data. Ther, the looped back port pointer data is checked for a
match witt> the value written into the P0rt Pointer Register
SEP 84
3-2