Hytera DMR - Page 529

5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
5VA
3V3D
5VA
MOD_H
MOD_L_RFCS
DAC_DIN
DAC_SCLK
DAC_FS
TV_APC
Final_bias
Ref
Ref
Ref
Title
Size Document Number Rev
Date: Sheet
of
<Doc> <RevCode>
<Title>
B
214Monday, November 29, 2010
Title
Size Document Number Rev
Date: Sheet of
<Doc> <RevCode>
<Title>
B
214Monday, November 29, 2010
Title
Size Document Number Rev
Date: Sheet of
<Doc> <RevCode>
<Title>
B
214Monday, November 29, 2010
DAC
DESIGNER LHY
C516
100P
C516
100P
R566 0R566 0
C500
33p
C500
33p
R513
100K
R513
100K
C406
4.7n
C406
4.7n
R570
5.1k
R570
5.1k
C501
330p
C501
330p
R512 10kR512 10k
C513
1000P
C513
1000P
R578
0
R578
0
R567 0R567 0
+
C511
10u/10v
+
C511
10u/10v
12
C510
100P
C510
100P
+
C508
10u/10V
+
C508
10u/10V
12
C512
0.1u
C512
0.1u
C525
nc
C525
nc
C506
0.01uF
C506
0.01uF
R508 0R508 0
R529 33KR529 33K
R500
100K
R500
100K
+
+
-
-
OUT
IN+
IN-
OUT
IN-
IN+
VEE
VCC
U501
OPAMP
+
+
-
-
OUT
IN+
IN-
OUT
IN-
IN+
VEE
VCC
U501
OPAMP
1
2
3
45
6
7
8
C475
4.7n
C475
4.7n
R505
0
R505
0
R502
1K
R502
1K
RN500 33*4RN500 33*4
1
2
3
4 5
6
7
8
C404
4.7n
C404
4.7n
C523
NC
C523
NC
R577
5.1k
R577
5.1k
U500
D/A IC
U500
D/A IC
DVDD
1
PD
2
LDAC
3
DIN
4
SCLK
5
CS
6
FS
7
DGND
8
AGND
9
REFINCD
10
OUTD
11
OUTC
12
OUTB
13
OUTA
14
REFINAB
15
AVDD
16
L500
BLM18PG600SN1
L500
BLM18PG600SN1
12
C507
0.01uF
C507
0.01uF
R572
4.7k
R572
4.7k
C403
4.7n
C403
4.7n
R528
68K
R528
68K
C524
NC
C524
NC
C518
100P
C518
100P
R506
10K
R506
10K
R573
5.6k
R573
5.6k
R568 5.1kR568 5.1k
C502
3300p
C502
3300p
R504 1KR504 1K
R503 1KR503 1K
R542 0R542 0
C521
NC
C521
NC
R574
NC
R574
NC
R510 10kR510 10k
+
C405
10uF/10V
+
C405
10uF/10V
12
C504
nc
C504
nc
C505
NC
C505
NC
R509 10kR509 10k
R564 0R564 0
C509
0.1u
C509
0.1u
C514 0.1uC514 0.1u
C471
0.1u
C471
0.1u
C522
NC
C522
NC
C515 0.1uC515 0.1u
R565 0R565 0
R507
0
R507
0
R501
10K
R501
10K
R575
5.1k
R575
5.1k
R514 100KR514 100K
R5691kR5691k
C503
1800PF
C503
1800PF
C517
100P
C517
100P
R5761k R5761k
519
MD78X/MD78XG Schematic Diagram
(DAC Circuit)