Need help?Do you have a question about the IDT 89HPES48T12G2 and is the answer not in the manual?
Overview of the user manual's purpose and scope.
Guidance on locating supplementary product details and specifications.
Outline of the manual's chapters and their respective topics.
Provides a high-level introduction to the PES48T12G2 device.
Details the key features and capabilities of the PES48T12G2 switch.
Lists and describes the functions of the PES48T12G2 pins, including multiplexed functions.
Provides a high-level overview of the PES48T12G2 architecture and its components.
Explains the logical view of a PCIe switch, including upstream and downstream ports and virtual PCI bus.
Provides an overview of the PES48T12G2's Switch Core functionality and services.
Describes the non-blocking crossbar design, ingress buffers, and egress buffers.
Details the IFB queues (Posted, Non-Posted, Completion) and their sizes.
Explains the EFBs for HOLB relief, packet re-ordering, and replay buffer functionality.
Covers reset and initialization procedures, including precedence and types of resets.
Explains the boot configuration vector sampled during a switch fundamental reset.
Details the cold and warm switch fundamental reset processes and their behavior.
Covers link operation adhering to PCI Express 2.0, supporting speeds and port merging.
Details support for 5.0 GT/s and 2.5 GT/s data rates per lane.
Discusses ASPM operation, including support for L0s and L1 states.
Describes the SerDes block, its functions, and per-lane programmability.
Details programmable SerDes transmitter settings like drive level and de-emphasis.
Discusses receiver equalizer for compensating channel loss and its controls.
Outlines guidelines for maximizing power savings in SerDes quads based on port state.
Describes the PES48T12G2-specific architectural behavior of the PCI Express switch.
Details the supported transaction routing types, including address and ID based routing.
Discusses ACS support as defined by PCI Express 2.0, focusing on downstream switch port operations.
Describes error conditions like physical, data-link, and transaction layer errors and how they are detected and handled.
Illustrates three hot-plug configurations for a PCIe switch application.
Lists and describes the hot-plug inputs and outputs supported via I/O expanders.
States that PES48T12G2 is hot-swap capable and meets specific requirements for I/Os.
Discusses power management capability structures and supported device power states.
Details the mechanisms for implementing PCI-Express power budgeting enhanced capability.
Introduces the 9 General Purpose I/O pins and their configuration options.
Summarizes the configuration of GPIO pins using registers like GPIOFUNC, GPIOCFG, and GPIOD.
Describes the two SMBus interfaces: Master and Slave, and their pin configurations.
Details the use of serial EEPROM for initializing software visible registers during switch fundamental reset.
Details programming the serial EEPROM via slave SMBus or a PCIe root.
Summarizes the pin mapping for I/O expanders 0 through 7 for hot-plug signals.
Lists supported SMBus transactions like Byte/Word Write/Read and Block Write/Read.
Explains multicast capability for forwarding a single TLP to multiple destinations.
Explains how multicast TLPs are forwarded to egress ports, differing from unicast rules.
Describes the 256 KB global address space for all software visible registers.
Outlines configuration space for PCI-to-PCI bridges, accessible as function 0.
Details Type 1 Configuration Header registers like Vendor ID, Device ID, and PCI Command.
Identifies PCI Express capability structures and points to the next capability.
Details the AER Enhanced Capability structure, including capabilities and status registers.
Controls switch behavior like reset halt, register unlock, and power budgeting data value unlock.
Details registers for controlling and monitoring SerDes blocks, requiring identification of associated SerDes.
Introduces JTAG Boundary Scan interface for testing interconnections after assembly.
Describes system logic using TAP controller, instruction register, and dedicated pins for various functions.
Explains the Instruction Register's role in selecting tests or accessing test registers via JTAG_TCK and TAP controller states.
Provides recommendations for driving JTAG pins and forcing the TAP controller into Test Logic-Reset.
To Next Page
General