Technical Reference Manual 002-29852 Rev. *B
Register Name Address Permission Description
PASS0_SAR1_CH0_RESULT
0x40901824 FULL Result data register
PASS0_SAR1_CH0_GRP_STAT
0x40901828 FULL Group status register
PASS0_SAR1_CH0_ENABLE
0x40901838 FULL Enable register
PASS0_SAR1_CH0_TR_CMD
0x4090183C FULL Software triggers
19.2.2 CH 1
Register Name Address Permission Description
PASS0_SAR1_CH1_TR_CTL
0x40901840 FULL Trigger control.
PASS0_SAR1_CH1_SAMPLE_CTL
0x40901844 FULL Sample control.
PASS0_SAR1_CH1_POST_CTL
0x40901848 FULL Post processing control
PASS0_SAR1_CH1_RANGE_CTL
0x4090184C FULL Range thresholds
PASS0_SAR1_CH1_INTR
0x40901850 FULL Interrupt request register.
PASS0_SAR1_CH1_INTR_SET
0x40901854 FULL Interrupt set request register
PASS0_SAR1_CH1_INTR_MASK
0x40901858 FULL Interrupt mask register.
PASS0_SAR1_CH1_INTR_MASKED
0x4090185C FULL Interrupt masked request register
PASS0_SAR1_CH1_WORK
0x40901860 FULL Working data register
PASS0_SAR1_CH1_RESULT
0x40901864 FULL Result data register
PASS0_SAR1_CH1_GRP_STAT
0x40901868 FULL Group status register
PASS0_SAR1_CH1_ENABLE
0x40901878 FULL Enable register
PASS0_SAR1_CH1_TR_CMD
0x4090187C FULL Software triggers
19.2.3 CH 2
Register Name Address Permission Description
PASS0_SAR1_CH2_TR_CTL
0x40901880 FULL Trigger control.
PASS0_SAR1_CH2_SAMPLE_CTL
0x40901884 FULL Sample control.
PASS0_SAR1_CH2_POST_CTL
0x40901888 FULL Post processing control
PASS0_SAR1_CH2_RANGE_CTL
0x4090188C FULL Range thresholds
PASS0_SAR1_CH2_INTR
0x40901890 FULL Interrupt request register.
PASS0_SAR1_CH2_INTR_SET
0x40901894 FULL Interrupt set request register
PASS0_SAR1_CH2_INTR_MASK
0x40901898 FULL Interrupt mask register.
PASS0_SAR1_CH2_INTR_MASKED
0x4090189C FULL Interrupt masked request register
PASS0_SAR1_CH2_WORK
0x409018A0 FULL Working data register
PASS0_SAR1_CH2_RESULT
0x409018A4 FULL Result data register
PASS0_SAR1_CH2_GRP_STAT
0x409018A8 FULL Group status register
PASS0_SAR1_CH2_ENABLE
0x409018B8 FULL Enable register
PASS0_SAR1_CH2_TR_CMD
0x409018BC FULL Software triggers
19.2.4 CH 3
Register Name Address Permission Description
PASS0_SAR1_CH3_TR_CTL
0x409018C0 FULL Trigger control.
PASS0_SAR1_CH3_SAMPLE_CTL
0x409018C4 FULL Sample control.
PASS0_SAR1_CH3_POST_CTL
0x409018C8 FULL Post processing control
PASS0_SAR1_CH3_RANGE_CTL
0x409018CC FULL Range thresholds
PASS0_SAR1_CH3_INTR
0x409018D0 FULL Interrupt request register.
PASS0_SAR1_CH3_INTR_SET
0x409018D4 FULL Interrupt set request register
PASS0_SAR1_CH3_INTR_MASK
0x409018D8 FULL Interrupt mask register.
PASS0_SAR1_CH3_INTR_MASKED
0x409018DC FULL Interrupt masked request register
PASS0_SAR1_CH3_WORK
0x409018E0 FULL Working data register
PASS0_SAR1_CH3_RESULT
0x409018E4 FULL Result data register
PASS0_SAR1_CH3_GRP_STAT
0x409018E8 FULL Group status register
PASS0_SAR1_CH3_ENABLE
0x409018F8 FULL Enable register
PASS0_SAR1_CH3_TR_CMD
0x409018FC FULL Software triggers
19.2.5 CH 4
Register Name Address Permission Description
PASS0_SAR1_CH4_TR_CTL
0x40901900 FULL Trigger control.
PASS0_SAR1_CH4_SAMPLE_CTL
0x40901904 FULL Sample control.
PASS0_SAR1_CH4_POST_CTL
0x40901908 FULL Post processing control
PASS0_SAR1_CH4_RANGE_CTL
0x4090190C FULL Range thresholds
PASS0_SAR1_CH4_INTR
0x40901910 FULL Interrupt request register.
PASS0_SAR1_CH4_INTR_SET
0x40901914 FULL Interrupt set request register
PASS0_SAR1_CH4_INTR_MASK
0x40901918 FULL Interrupt mask register.
PASS0_SAR1_CH4_INTR_MASKED
0x4090191C FULL Interrupt masked request register
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers