Infineon TRAVEO T2G - 19.5.2 EPASS_MMIO; 19.5.2.1 PASS_PASS_CTL

Technical Reference Manual 002-29852 Rev. *B
19.5.2 EPASS_MMIO
19.5.2.1 PASS_PASS_CTL
Description:
PASS control register
Address:
0x409F0000
Offset:
0x0
Retention:
Retained
IsDeepSleep:
No
Comment:
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:6] SUPPLY
_MON_LVL
_B [5:5]
SUPPLY
_MON_EN
_B [4:4]
None [3:2] SUPPLY
_MON_LVL
_A [1:1]
SUPPLY
_MON_EN
_A [0:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:8]
Bits 23 22 21 20 19 18 17 16
Name None
[23:23]
REFBUF_MODE [22:21] None [20:16]
Bits 31 30 29 28 27 26 25 24
Name DBG_FREEZE_EN [31:28] None [27:24]
Bit-fields
Bits
Name SW HW Default or
Enum
Description
0 SUPPLY_MON_EN_A RW R 0 Supply monitor enable for AMUXBUS_A
(amuxbus_a_mon)
1 SUPPLY_MON_LVL_A RW R 0 Supply monitor level select for AMUXBUS_A
VRL 0 amuxbus_a_mon = VRL
VRH 1 amuxbus_a_mon = VRH
4 SUPPLY_MON_EN_B RW R 0 Supply monitor enable for AMUXBUS_B
(amuxbus_b_mon)
5 SUPPLY_MON_LVL_B RW R 0 Supply monitor level select for AMUXBUS_B
VRL 0 amuxbus_b_mon = VRL
VRH 1 amuxbus_b_mon = VRH
21:22 REFBUF_MODE RW R 0 Reference mode.
The reference needs to be present when using TEMP
sensor or diagnostic reference (in addition to
SAR.DIAG_CTL.DIAG_EN).
Note that setting this mode is not required for the ADC
operation itself.
OFF 0 No reference
ON 1 Reference = buffered Vbg from SRSS
RESERVED 2 undefined
BYPASS 3 Reference = unbuffered Vbg from SRSS
28:31 DBG_FREEZE_EN RW R 0 Debug pause enable, 1 per ADC.
When set a high tr_debug_freeze trigger will prevent
the scheduler from starting acquisitions on a new
channel. Note that averaging for an already started
channel will be completed.
1124
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers