Technical Reference Manual 002-29852 Rev. *B
20.30.7 PERI_DIV_24_5_CTL
Description:
Divider control (for 24.5 divider)
Address:
0x40001C00
Offset:
0x1C00
Retention:
Retained
IsDeepSleep:
No
Comment:
Largest of the divider types.
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name FRAC5_DIV [7:3] None [2:1] EN [0:0]
Bits 15 14 13 12 11 10 9 8
Name INT24_DIV [15:8]
Bits 23 22 21 20 19 18 17 16
Name INT24_DIV [23:16]
Bits 31 30 29 28 27 26 25 24
Name INT24_DIV [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0 EN R RW 0 Divider enabled. HW sets this field to '1' as a result of
an ENABLE command. HW sets this field to '0' as a
result on a DISABLE command.
Note that this field is retained. As a result, the divider
does NOT have to be re-enabled after transitioning
from DeepSleep to Active power mode.
3:7 FRAC5_DIV RW R 0 Fractional division by (FRAC5_DIV/32). Allows for
fractional divisions in the range [0, 31/32]. Note that
fractional division results in clock jitter as some clock
periods may be 1 'clk_peri' cycle longer than other
clock periods.
Note that this field is retained. However, the counter
that is used to implement the division is not and will be
initialized by HW to '0' when transitioning from
DeepSleep to Active power mode.
8:31 INT24_DIV RW R 0 Integer division by (1+INT24_DIV). Allows for integer
divisions in the range [1, 16,777,216]. Note: combined
with fractional division, this divider type allows for a
division in the range [1, 16,777,216 31/32] in 1/32
increments.
For the generation of a divided clock, the integer
division range is restricted to [2, 16,777,216 31/32].
For the generation of a 50/50 percent duty cycle
divided clock, the division range is restricted to [2,
16,777,216].
Note that this field is retained. However, the counter
that is used to implement the division is not and will be
initialized by HW to '0' when transitioning from
DeepSleep to Active power mode.
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers
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