Infineon TRAVEO T2G - 20.30.9 GR; 20.30.9.1 PERI_GR_CLOCK_CTL

Technical Reference Manual 002-29852 Rev. *B
20.30.9 GR
20.30.9.1 PERI_GR_CLOCK_CTL
Description:
Clock control
Address:
0x40004000
Offset:
0x0
Retention:
Retained
IsDeepSleep:
No
Comment:
The peripheral interconnect supports up to sixteen groups: group 0, group 1, ..., group 15.
Peripheral groups 0, 1 and 2 use clk_slow (clk_group[0] = clk_group[1] = clk_group[2] =
clk_slow) and do NOT have a CLOCK_GROUP_DIV_CTL register. Peripheral groups 3, 4, ...,
15 have a dedicated CLOCK_GROUP_DIV_CTL register.
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:0]
Bits 15 14 13 12 11 10 9 8
Name INT8_DIV [15:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
8:15 INT8_DIV RW R 0 Specifies a group clock divider (from the peripheral
clock 'clk_peri' to the group clock
'clk_group[3/4/5/...15]'). Integer division by
(1+INT8_DIV). Allows for integer divisions in the range
[1, 256].
Note that this field is retained. However, the counter
that is used to implement the division is not and will be
initialized by HW to '0' when transitioning from
DeepSleep to Active power mode.
1150
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers