Infineon TRAVEO T2G - 23.9.49 SCB_INTR_RX

Technical Reference Manual 002-29852 Rev. *B
23.9.49 SCB_INTR_RX
Description:
Receiver interrupt request
Address:
0x40600FC0
Offset:
0xFC0
Retention:
Not Retained
IsDeepSleep:
No
Comment:
The register fields are not retained In DeepSleep power mode: HW clears the interrupt causes
to '0', when coming out of DeepSleep power mode. In addition, HW clears the interrupt causes
to '0', when the IP is disabled. As a result, the interrupt causes are only available in
Active/Sleep power modes; they are generated by internally clocked logic (this logic operates
on a clock that is only available in Active/Sleep power modes).
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name BLOCKED
[7:7]
UNDERFLOW
[6:6]
OVERFLOW
[5:5]
None [4:4] FULL [3:3] NOT
_EMPTY
[2:2]
None [1:1] TRIGGER
[0:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:12] BREAK
_DETECT
[11:11]
BAUD
_DETECT
[10:10]
PARITY
_ERROR
[9:9]
FRAME
_ERROR
[8:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0 TRIGGER RW1C RW1S 0 More entries in the RX FIFO than the value specified
by RX_FIFO_CTRL.TRIGGER_LEVEL.
Only used in FIFO mode.
2 NOT_EMPTY RW1C RW1S 0 RX FIFO is not empty.
Only used in FIFO mode.
3 FULL RW1C RW1S 0 RX FIFO is full. Note that received data frames are lost
when the RX FIFO is full. Dependent on
CTRL.MEM_WIDTH: (FF_DATA_NR =
EZ_DATA_NR/2)
MEM_WIDTH is '0': # entries == FF_DATA_NR.
MEM_WIDTH is '1': # entries == FF_DATA_NR/2.
MEM_WIDTH is '2': # entries == FF_DATA_NR/4.
Only used in FIFO mode.
5 OVERFLOW RW1C RW1S 0 Attempt to write to a full RX FIFO. Note: in I2C mode,
the OVERFLOW is set when a data frame is received
and the RX FIFO is full, independent of whether it is
ACK'd or NACK'd.
Only used in FIFO mode.
6 UNDERFLOW RW1C RW1S 0 Attempt to read from an empty RX FIFO.
Only used in FIFO mode.
1450
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers