Technical Reference Manual 002-29852 Rev. *B
28.4.1.1.15 TCPWM_GRP_CNT_TR_IN_SEL1
Description:
Counter input trigger selection register 1
Address:
0x40380048
Offset:
0x48
Retention:
Retained
IsDeepSleep:
No
Comment:
Used to select triggers for specific counter events.
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name START_SEL [7:0]
Bits 15 14 13 12 11 10 9 8
Name CAPTURE1_SEL [15:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:7 START_SEL RW R 0 Selects one of the 256 input triggers as a start trigger.
In QUAD mode, this is the second phase (phi B).
8:15 CAPTURE1_SEL RW R 0 Selects one of the 256 input triggers as a capture 1
trigger.
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers