Technical Reference Manual 002-29852 Rev. *B
4.13.2 DWT
4.13.2.1 CM4_DWT_CTRL
Description:
Control register
Address:
0xE0001000
Offset:
0x0
Retention:
Retained
IsDeepSleep:
No
Comment:
The CTRL register characteristics are:
Purpose: Provides configuration and status information for the DWT unit, and used to control
features of the unit.
Usage constraints: There are no usage constraints.
Configurations: Always implemented.
Attributes: See Table C1-21 and the register field descriptions.
Default:
0x40000000
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name POSTPRESET [4:1] CYCCNTENA
[0:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:13] PCSAMPLEN
A [12:12]
SYNCTAP [11:10] CYCTAP
[9:9]
POSTINIT
[8:8]
Bits 23 22 21 20 19 18 17 16
Name None
[23:23]
CYCEVTENA
[22:22]
FOLDEVTEN
A [21:21]
LSUEVTENA
[20:20]
SLEEPEVTE
NA [19:19]
EXCEVTENA
[18:18]
CPIEVTENA
[17:17]
EXCTRCENA
[16:16]
Bits 31 30 29 28 27 26 25 24
Name NUMCOMP [31:28] NOTRCPKT
[27:27]
NOEXTTRIG
[26:26]
NOCYCCNT
[25:25]
NOPRFCNT
[24:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0 CYCCNTENA RW R 0 Enables CYCCNT:
0 Disabled.
1 Enabled.
This bit is UNK/SBZP if the NOCYCCNT bit is RAO.
1:4 POSTPRESET RW R 0 Reload value for the POSTCNT counter. For more
information see The POSTCNT timer on Arm TRM
page C1-792.
This field is UNK/SBZP if the NOCYCCNT bit is RAO.
5:8 POSTINIT RW R 0 Initial value for the POSTCNT counter. For more
information see Enabling POSTCNT, and behavior of
accesses to the DWT_CTRL.POSTINIT field and The
POSTCNT timer on Arm TRM page C1-792.
This field is UNK/SBZP if the NOCYCCNT bit is RAO.
Note
This field was previously called POSTCNT. The
changed name gives a better indication of its function.
9 CYCTAP RW R 0 Selects the position of the POSTCNT tap on the
CYCCNT counter:
0 POSTCNT tap at CYCCNT[6].
1 POSTCNT tap at CYCCNT[10].
For more information see The POSTCNT timer on
page C1-792.
This bit is UNK/SBZP if the NOCYCCNT bit is RAO.
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers
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