Infineon TRAVEO T2G - 4.13.2.8 CM4_DWT_PCSR

Technical Reference Manual 002-29852 Rev. *B
4.13.2.8 CM4_DWT_PCSR
Description:
Program Counter Sample Register
Address:
0xE000101C
Offset:
0x1C
Retention:
Retained
IsDeepSleep:
No
Comment:
The PCSR characteristics are:
Purpose: Samples the current value of the program counter.
Usage constraints: There are no usage constraints.
Note: Bit[0] of any sampled value is RAZ and does not reflect instruction set state as it does in
a PC sample on the ARMv7-A and ARMv7-R architecture profiles.
Configurations: An optional feature. Register is RAZ/WI if not implemented.
Attributes: See Table C1-21 on Arm TRM page C1-797.
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name EIASAMPLE [7:0]
Bits 15 14 13 12 11 10 9 8
Name EIASAMPLE [15:8]
Bits 23 22 21 20 19 18 17 16
Name EIASAMPLE [23:16]
Bits 31 30 29 28 27 26 25 24
Name EIASAMPLE [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:31 EIASAMPLE RW RW 0 Executed Instruction Address sample value.
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2022-04-18
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