Infineon TRAVEO T2G - 5.1 Register Details; 5.1.1 CPUSS_IDENTITY

Technical Reference Manual 002-29852 Rev. *B
5.1 Register Details
5.1.1 CPUSS_IDENTITY
Description:
Identity
Address:
0x40200000
Offset:
0x0
Retention:
Not Retained
IsDeepSleep:
No
Comment:
This register is typically used by SW that is executed on different bus masters or with different
protection contexts.
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name PC [7:4] None [3:2] NS [1:1] P [0:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:12] MS [11:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0 P R W Undefined This field specifies the privileged setting ('0': user
mode; '1': privileged mode) of the transfer that reads
the register.
1 NS R W Undefined This field specifies the security setting ('0': secure
mode; '1': non-secure mode) of the transfer that reads
the register.
4:7 PC R W Undefined This field specifies the protection context of the
transfer that reads the register.
8:11 MS R W Undefined This field specifies the bus master identifier of the
transfer that reads the register.
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2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers