Infineon TRAVEO T2G - 5.1.52 CPUSS_TRIM_ROM_CTL

Technical Reference Manual 002-29852 Rev. *B
5.1.52 CPUSS_TRIM_ROM_CTL
Description:
ROM trim control
Address:
0x40202100
Offset:
0x2100
Retention:
Retained
IsDeepSleep:
No
Comment:
This register is used to trim ALL ROM memories in the device. Different operating Voltages
may require different trim settings.
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name TRIM [7:0]
Bits 15 14 13 12 11 10 9 8
Name TRIM [15:8]
Bits 23 22 21 20 19 18 17 16
Name TRIM [23:16]
Bits 31 30 29 28 27 26 25 24
Name TRIM [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:31 TRIM RW R ROM_TRIM
_DEFAULT
For ARM ROMs the bits are defined as follows
[2:0] EMA: Extra Margin Adjustment (0 is the fastest
setting)
Recommended default value: EMA=2
(ROM_TRIM_DEFAULT=0x0000_0002,
ROM_TRIM_WIDTH=3)
For Synopsys ROMs the bits are defined as follows:
[3:0] RM: Read-Write margin control. This is used for
setting the Read-Write margin. It programs the sense
amplifier differential setting and allows the trade off
between speed and robustness.
- RM[1:0] values control access time and cycle time of
the memory. RM[1:0] = '0' is the slowest possible
mode of operation for the memory. This setting is
required for VDDMIN operation.
- RM[3:2] are factory pins reserved for debug mode
and should be set to '0'.
[4] RME: Read-Write margin enable control. This
selects between the default Read-Write margin setting,
and the external pin Read-Write margin setting.
Recommended default value for LP: RME=1, RM=2
(ROM_TRIM_DEFAULT=0x0000_0012,
ROM_TRIM_WIDTH=5)
Recommended default value for ULP: RME=1, RM=3
(ROM_TRIM_DEFAULT=0x0000_0013,
ROM_TRIM_WIDTH=5)
755
2022-04-18
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