Infineon TRAVEO T2G - 5.1.53 CPUSS_TRIM_RAM_CTL

Technical Reference Manual 002-29852 Rev. *B
5.1.53 CPUSS_TRIM_RAM_CTL
Description:
RAM trim control
Address:
0x40202104
Offset:
0x2104
Retention:
Retained
IsDeepSleep:
No
Comment:
This register is used to trim ALL RAM memories in the device. Different operating Voltages
may require different trim settings.
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name TRIM [7:0]
Bits 15 14 13 12 11 10 9 8
Name TRIM [15:8]
Bits 23 22 21 20 19 18 17 16
Name TRIM [23:16]
Bits 31 30 29 28 27 26 25 24
Name TRIM [31:24]
Bit-fields
756
2022-04-18
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