Infineon TRAVEO T2G - 5.1.55 CPUSS_CM4_SYSTEM_INT_CTL

Technical Reference Manual 002-29852 Rev. *B
5.1.55 CPUSS_CM4_SYSTEM_INT_CTL
Description:
CM4 system interrupt control
Address:
0x4020A000
Offset:
0xA000
Retention:
Retained
IsDeepSleep:
No
Comment:
Only present when SYSTEM_IRQ_PRESENT is '1'
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:3] CPU_INT_IDX [2:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name CPU_INT
_VALID
[31:31]
None [30:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:2 CPU_INT_IDX RW R Undefined N/A
31 CPU_INT_VALID RW R 0 N/A
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2022-04-18
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