Infineon TRAVEO T2G - 8 DMAC; 8.1 CH 0; 8.2 CH 1; 8.3 CH 2

Technical Reference Manual 002-29852 Rev. *B
8 DMAC
Description
DMAC
Base Address
0x402A0000
Size
0x10000
Slave Num
MMIO2 - 9
Register Name
Address Permission Description
DMAC_CTL
0x402A0000 FULL Control
DMAC_ACTIVE
0x402A0008 FULL Active channels
8.1 CH 0
Register Name
Address Permission Description
DMAC_CH0_CTL
0x402A1000 FULL Channel control
DMAC_CH0_IDX
0x402A1010 FULL Channel current indices
DMAC_CH0_SRC
0x402A1014 FULL Channel current source address
DMAC_CH0_DST
0x402A1018 FULL Channel current destination address
DMAC_CH0_CURR
0x402A1020 FULL Channel current descriptor pointer
DMAC_CH0_TR_CMD
0x402A1028 FULL Channle software trigger
DMAC_CH0_DESCR_STATUS
0x402A1040 FULL Channel descriptor status
DMAC_CH0_DESCR_CTL
0x402A1060 FULL Channel descriptor control
DMAC_CH0_DESCR_SRC
0x402A1064 FULL Channel descriptor source
DMAC_CH0_DESCR_DST
0x402A1068 FULL Channel descriptor destination
DMAC_CH0_DESCR_X_SIZE
0x402A106C FULL Channel descriptor X size
DMAC_CH0_DESCR_X_INCR
0x402A1070 FULL Channel descriptor X increment
DMAC_CH0_DESCR_Y_SIZE
0x402A1074 FULL Channel descriptor Y size
DMAC_CH0_DESCR_Y_INCR
0x402A1078 FULL Channel descriptor Y increment
DMAC_CH0_DESCR_NEXT
0x402A107C FULL Channel descriptor next pointer
DMAC_CH0_INTR
0x402A1080 FULL Interrupt
DMAC_CH0_INTR_SET
0x402A1084 FULL Interrupt set
DMAC_CH0_INTR_MASK
0x402A1088 FULL Interrupt mask
DMAC_CH0_INTR_MASKED
0x402A108C FULL Interrupt masked
8.2 CH 1
Register Name Address Permission Description
DMAC_CH1_CTL
0x402A1100 FULL Channel control
DMAC_CH1_IDX
0x402A1110 FULL Channel current indices
DMAC_CH1_SRC
0x402A1114 FULL Channel current source address
DMAC_CH1_DST
0x402A1118 FULL Channel current destination address
DMAC_CH1_CURR
0x402A1120 FULL Channel current descriptor pointer
DMAC_CH1_TR_CMD
0x402A1128 FULL Channle software trigger
DMAC_CH1_DESCR_STATUS
0x402A1140 FULL Channel descriptor status
DMAC_CH1_DESCR_CTL
0x402A1160 FULL Channel descriptor control
DMAC_CH1_DESCR_SRC
0x402A1164 FULL Channel descriptor source
DMAC_CH1_DESCR_DST
0x402A1168 FULL Channel descriptor destination
DMAC_CH1_DESCR_X_SIZE
0x402A116C FULL Channel descriptor X size
DMAC_CH1_DESCR_X_INCR
0x402A1170 FULL Channel descriptor X increment
DMAC_CH1_DESCR_Y_SIZE
0x402A1174 FULL Channel descriptor Y size
DMAC_CH1_DESCR_Y_INCR
0x402A1178 FULL Channel descriptor Y increment
DMAC_CH1_DESCR_NEXT
0x402A117C FULL Channel descriptor next pointer
DMAC_CH1_INTR
0x402A1180 FULL Interrupt
DMAC_CH1_INTR_SET
0x402A1184 FULL Interrupt set
DMAC_CH1_INTR_MASK
0x402A1188 FULL Interrupt mask
DMAC_CH1_INTR_MASKED
0x402A118C FULL Interrupt masked
8.3 CH 2
Register Name Address Permission Description
DMAC_CH2_CTL
0x402A1200 FULL Channel control
DMAC_CH2_IDX
0x402A1210 FULL Channel current indices
DMAC_CH2_SRC
0x402A1214 FULL Channel current source address
DMAC_CH2_DST
0x402A1218 FULL Channel current destination address
DMAC_CH2_CURR
0x402A1220 FULL Channel current descriptor pointer
800
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers