Technical Reference Manual 002-29852 Rev. *B
Register Name Address Permission Description
DW0_CH_STRUCT56_CH_CURR_PTR
0x40288E0C FULL Channel current descriptor pointer
DW0_CH_STRUCT56_INTR
0x40288E10 FULL Interrupt
DW0_CH_STRUCT56_INTR_SET
0x40288E14 FULL Interrupt set
DW0_CH_STRUCT56_INTR_MASK
0x40288E18 FULL Interrupt mask
DW0_CH_STRUCT56_INTR_MASKED
0x40288E1C FULL Interrupt masked
DW0_CH_STRUCT56_SRAM_DATA0
0x40288E20 FULL SRAM data 0
DW0_CH_STRUCT56_SRAM_DATA1
0x40288E24 FULL SRAM data 1
DW0_CH_STRUCT56_TR_CMD
0x40288E28 FULL Channel software trigger
9.1.1.58 CH_STRUCT 57
Register Name Address Permission Description
DW0_CH_STRUCT57_CH_CTL
0x40288E40 FULL Channel control
DW0_CH_STRUCT57_CH_STATUS
0x40288E44 FULL Channel status
DW0_CH_STRUCT57_CH_IDX
0x40288E48 FULL Channel current indices
DW0_CH_STRUCT57_CH_CURR_PTR
0x40288E4C FULL Channel current descriptor pointer
DW0_CH_STRUCT57_INTR
0x40288E50 FULL Interrupt
DW0_CH_STRUCT57_INTR_SET
0x40288E54 FULL Interrupt set
DW0_CH_STRUCT57_INTR_MASK
0x40288E58 FULL Interrupt mask
DW0_CH_STRUCT57_INTR_MASKED
0x40288E5C FULL Interrupt masked
DW0_CH_STRUCT57_SRAM_DATA0
0x40288E60 FULL SRAM data 0
DW0_CH_STRUCT57_SRAM_DATA1
0x40288E64 FULL SRAM data 1
DW0_CH_STRUCT57_TR_CMD
0x40288E68 FULL Channel software trigger
9.1.1.59 CH_STRUCT 58
Register Name Address Permission Description
DW0_CH_STRUCT58_CH_CTL
0x40288E80 FULL Channel control
DW0_CH_STRUCT58_CH_STATUS
0x40288E84 FULL Channel status
DW0_CH_STRUCT58_CH_IDX
0x40288E88 FULL Channel current indices
DW0_CH_STRUCT58_CH_CURR_PTR
0x40288E8C FULL Channel current descriptor pointer
DW0_CH_STRUCT58_INTR
0x40288E90 FULL Interrupt
DW0_CH_STRUCT58_INTR_SET
0x40288E94 FULL Interrupt set
DW0_CH_STRUCT58_INTR_MASK
0x40288E98 FULL Interrupt mask
DW0_CH_STRUCT58_INTR_MASKED
0x40288E9C FULL Interrupt masked
DW0_CH_STRUCT58_SRAM_DATA0
0x40288EA0 FULL SRAM data 0
DW0_CH_STRUCT58_SRAM_DATA1
0x40288EA4 FULL SRAM data 1
DW0_CH_STRUCT58_TR_CMD
0x40288EA8 FULL Channel software trigger
9.1.1.60 CH_STRUCT 59
Register Name Address Permission Description
DW0_CH_STRUCT59_CH_CTL
0x40288EC0 FULL Channel control
DW0_CH_STRUCT59_CH_STATUS
0x40288EC4 FULL Channel status
DW0_CH_STRUCT59_CH_IDX
0x40288EC8 FULL Channel current indices
DW0_CH_STRUCT59_CH_CURR_PTR
0x40288ECC FULL Channel current descriptor pointer
DW0_CH_STRUCT59_INTR
0x40288ED0 FULL Interrupt
DW0_CH_STRUCT59_INTR_SET
0x40288ED4 FULL Interrupt set
DW0_CH_STRUCT59_INTR_MASK
0x40288ED8 FULL Interrupt mask
DW0_CH_STRUCT59_INTR_MASKED
0x40288EDC FULL Interrupt masked
DW0_CH_STRUCT59_SRAM_DATA0
0x40288EE0 FULL SRAM data 0
DW0_CH_STRUCT59_SRAM_DATA1
0x40288EE4 FULL SRAM data 1
DW0_CH_STRUCT59_TR_CMD
0x40288EE8 FULL Channel software trigger
9.1.1.61 CH_STRUCT 60
Register Name Address Permission Description
DW0_CH_STRUCT60_CH_CTL
0x40288F00 FULL Channel control
DW0_CH_STRUCT60_CH_STATUS
0x40288F04 FULL Channel status
DW0_CH_STRUCT60_CH_IDX
0x40288F08 FULL Channel current indices
DW0_CH_STRUCT60_CH_CURR_PTR
0x40288F0C FULL Channel current descriptor pointer
DW0_CH_STRUCT60_INTR
0x40288F10 FULL Interrupt
DW0_CH_STRUCT60_INTR_SET
0x40288F14 FULL Interrupt set
DW0_CH_STRUCT60_INTR_MASK
0x40288F18 FULL Interrupt mask
DW0_CH_STRUCT60_INTR_MASKED
0x40288F1C FULL Interrupt masked
DW0_CH_STRUCT60_SRAM_DATA0
0x40288F20 FULL SRAM data 0
DW0_CH_STRUCT60_SRAM_DATA1
0x40288F24 FULL SRAM data 1
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers