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Inovance H3U Series
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205
4
4 Instructions 4.5.4 Data Rotation and Shift
Operands
Operand
Bit Element Word Element
System·User System·User Bit Designation Indexed Address Constant
Real
Number
S X Y M T C S SM D R T C SD KnX KnY KnM KnS KnSM
V,Z
Modication K H E
D X Y M T C S SM D R T C SD KnX KnY KnM KnS KnSM
V,Z
Modication K H E
n X Y M T C S SM D R T C SD KnX KnY KnM KnS KnSM
V,Z
Modication K H E
Note: The elements in gray background are supported.
Function
The rst piece of data in the FIFO queue (S) is read. The data within the queue is subsequently moved one
word to the right to ll the read area, and the queue pointer is decremented by 1. The read data is written
to D. The operand with the rst number stores a pointer. When the instruction is executed, the pointer is
decremented by 1 and then the content of the source operand specied by S is written to the FIFO queue
specied by D. The position of insertion into the queue is specied by the pointer. If the pointer is 0, the
preceding operation is not performed and the zero ag M8020 is set to 1 to identify this situation.
The instruction of the pulse execution type is generally used.
Example:
Indicator
FIFO data write instruction
X
0
D
1
D 2D
3
D
4
D
5
D
6
D 7
D
8
D 9D 10
ǒSFRDP D1 D20 K10Ǔ
S
D
n
D
20
When X0 switches from OFF to ON, this instruction acts in the
following sequence (the content of D10 unchanged):
1. The content of D2 is read and transferred to D20.
2. D10 to D3 are shifted one register to the right.
3. The value of pointer D1 is decremented by 1.
SFR: 16-bit data shift right with carry by n bits
Overview
The SFR instruction shifts the 16 bits of a word element to the right by n bit places.
SFR S n
16-bit data shift right
with carry by n bits
Applicable model:
H3U
S
Word to be
shifted
Number of the element that stores the data to be shifted
16-bit instruction (5 steps)
SFR: Continuous
execution
SFRP: Pulse execution
n Shift times Number of shift times; value range: 0 ≤ n ≤ 15
Operands
Operand
Bit Element Word Element
System·User System·User Bit Designation Indexed Address Constant
Real
Number
S
X Y M T C S SM D R T C SD KnX KnY KnM KnS KnSM V
and
Z Modication K H E
n
X Y M T C S SM D R T C SD KnX KnY KnM KnS KnSM V
and
Z Modication K H E
Note: The elements in gray background are supported.

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