Intel 6 SERIES CHIPSET - DATASHEET 01-2011 - Page 394

Chipset Configuration Registers
394 Datasheet
10.1.49 PM_CFG—Power Management Configuration
Offset Address: 3318–331Bh Attribute: R/W
Default Value: 00000000h Size: 32-bit
Bit Description
31:27 Reserved.
26:24 PM_CFG Field 1 — R/W. BIOS must program this field to 101b.
23:22 Reserved.
21
RTC Wake from Deep S4/S5 Disable (RTC_DS_WAKE_DIS)— R/W. When set,
this bit disables RTC wakes from waking the system from Deep S4/S5.
This bit is reset by RTCRST#.
20 Reserved.
19:18
SLP_SUS# Minimum Assertion Width (SLP_SUS_MIN_ASST_WDTH)— R/W.
This field indicates the minimum assertion width of the SLP_SUS# signal to
guarantee that the SUS power supplies have been fully power cycled. This value may
be modified per platform depending on power supply capacitance, board capacitance,
power circuits, etc.
Valid values are:
11 = 4 seconds
10 = 1 second
01 = 500 ms
00 = 0 ms (that is, stretching disabled - default)
These bits are cleared by RTCRST# assertion.
NOTES:
1. This field is RO when the SLP Stretching Policy Lock-Down bit is set.
2. This field is ignored when exiting G3 or Deep S4/S5 states if the “Disable SLP
Stretching After SUS Well Power Up” bit is set. Note that unlike with all other
SLP_* pin stretching, this disable bit only impacts SLP_SUS# stretching
during G3 exit rather than both G3 and Deep S4/S5 exit. SLP_SUS#
stretching always applies to Deep S4/S5 regardless of the disable bit.
3. For platforms that enable Deep S4/S5, BIOS must program SLP_SUS#
stretching to be greater than or equal to the largest stretching value on any
other SLP_* pin (SLP_S3#, SLP_S4#, or SLP_A#).
17:16
SLP_A# Minimum Assertion Width (SLP_A_MIN_ASST_WDTH) — R/W. This
field indicates the minimum assertion width of the SLP_A# signal to guarantee that
the ASW power supplies have been fully power cycled. This value may be modified
per platform depending on power supply capacitance, board capacitance, power
circuits, etc.
Valid values are:
11 = 2 seconds
10 = 98 ms
01 = 4 seconds
00 = 0 ms (that is, stretching disabled – default)
These bits are cleared by RTCRST# assertion.
NOTES:
1. This field is RO when the SLP Stretching Policy Lock-Down bit is set.
2. This field is ignored when exiting G3 or Deep S4/S5 states if the “Disable SLP
Stretching After SUS Well Power Up” bit is set.
15:0 Reserved.