Intel 6 SERIES CHIPSET - DATASHEET 01-2011 - Page 395

Datasheet 395
Chipset Configuration Registers
10.1.50 CIR8—Chipset Initialization Register 8
Offset Address: 3324–3327h Attribute: R/W
Default Value: 00000000h Size: 32-bit
10.1.51 DEEP_S4_POL—Deep S4 Power Policies
Offset Address: 332C–332Fh Attribute: R/W
Default Value: 00000000h Size: 32-bit
This register is in the RTC power well and is reset by RTCRST# assertion.
10.1.52 DEEP_S5_POL—Deep S5 Power Policies
Offset Address: 3330–3333h Attribute: R/W
Default Value: 00000000h Size: 32-bit
This register is in the RTC power well and is reset by RTCRST# assertion.
10.1.53 CIR10—Chipset Initialization Register 10
Offset Address: 3340–3343h Attribute: R/W
Default Value: 00000000h Size: 32-bit
Bit Description
31:0 CIR8 Field 1 — R/W. BIOS must program this field to 04000000h.
Bit Description
31:2 Reserved.
1
Deep S4 Enable in DC Mode (DPS4_EN_DC) — R/W. A '1' in this bit enables the
platform to enter Deep S4 while operating on DC power (based on the AC_PRESENT
pin value).
0
Deep S4 Enable in AC Mode (DPS4_EN_AC) — R/W. A '1' in this bit enables the
platform to enter Deep S4 while operating on AC power (based on the AC_PRESENT
pin value). Required to be programmed to 0 on mobile.
Bit Description
31:16 Reserved.
15
Deep S5 Enable in DC Mode (DPS5_EN_DC) — R/W. A '1' in this bit enables the
platform to enter Deep S5 while operating on DC power (based on the AC_PRESENT
pin value).
14
Deep S5 Enable in AC Mode (DPS5_EN_AC) — R/W. A '1' in this bit enables the
platform to enter Deep S5 while operating on AC power (based on the AC_PRESENT
pin value). Required to be programmed to 0 on mobile.
13:0 Reserved.
Bit Description
31:20 Reserved
19:0 CIR10 Field 1 — R/W. BIOS must program this field to FFFFFh.