Intel 6 SERIES CHIPSET - DATASHEET 01-2011 - Page 398

Chipset Configuration Registers
398 Datasheet
10.1.63 CIR17—Chipset Initialization Register 17
Offset Address: 33A0–33A3h Attribute: R/W
Default Value: 00000000h Size: 32-bit
10.1.64 CIR23—Chipset Initialization Register 23
Offset Address: 33B0–33B3h Attribute: R/W
Default Value: 00000000h Size: 32-bit
10.1.65 CIR19—Chipset Initialization Register 19
Offset Address: 33C0–33C3h Attribute: R/W
Default Value: 00000000h Size: 32-bit
10.1.66 PMSYNC Configuration
Offset Address: 33C8–33CBh Attribute: R/W
Default Value: 00000000h Size: 32-bit
Bit Description
31:0 CIR17 Field 1 — R/W. BIOS must program this field to 00000800h.
Bit Description
31:0 CIR23 Field 1 — R/W. BIOS must program this field to 00001000h.
Bit Description
31:0 CIR19 Field 1 — R/W. BIOS must program this field to 00093900h.
Bit Description
31:12 Reserved
11
GPIO_D Pin Selection (GPIO_D_SEL) — R/W. There are two possible GPIOs that
can be routed to the GPIO_D PMSYNC state. This bit selects between them:
0 = GPIO5 (default)
1 = GPIO0
10
GPIO_C Pin Selection (GPIO_C_SEL) — R/W. There are two possible GPIOs that
can be routed to the GPIO_C PMSYNC state. This bit selects between them:
0 = GPIO37 (default)
1 = GPIO4
9
GPIO_B Pin Selection (GPIO_B_SEL) — R/W. There are two possible GPIOs that
can be routed to the GPIO_B PMSYNC state. This bit selects between them:
0 = GPIO0 (default)
1 = GPIO37
8
GPIO_A Pin Selection (GPIO_A_SEL) — R/W. There are two possible GPIOs that
can be routed to the GPIO_A PMSYNC state. This bit selects between them:
0 = GPIO4 (default)
1 = GPIO5
7:0 Reserved