Intel 6 SERIES CHIPSET - DATASHEET 01-2011 - Page 399

Datasheet 399
Chipset Configuration Registers
10.1.67 CIR20—Chipset Initialization Register 20
Offset Address: 33CC–33CFh Attribute: R/W
Default Value: 00000000h Size: 32-bit
10.1.68 CIR21—Chipset Initialization Register 21
Offset Address: 33D0–33D3h Attribute: R/W
Default Value: 00000000h Size: 32-bit
10.1.69 CIR22—Chipset Initialization Register 22
Offset Address: 33D4–33D7h Attribute: R/W
Default Value: 00000000h Size: 32-bit
Bit Description
31:0 CIR20 Field 1 — R/W. BIOS must program this field to 24653002h.
Bit Description
31:0 CIR21 Field 1 — R/W. BIOS must program this field to 062108E7h.
Bit Description
31
GPIO_D to PMSYNC Enable (GPIO_D_PMSYNC_EN) — R/W.
0 = GPIO_D (as selected in RCBA+33C8h) pin state not sent to processor over
PMSYNC.
1 = GPIO_D state sent to processor over PMSYNC.
30
GPIO_C to PMSYNC Enable (GPIO_C_PMSYNC_EN) — R/W.
0 = GPIO_C (as selected in) pin state not sent to processor over PMSYNC.
1 = GPIO_C state sent to processor over PMSYNC.
29
GPIO_B to PMSYNC Enable (GPIO_B_PMSYNC_EN) — R/W.
0 = GPIO_B (as selected in) pin state not sent to processor over PMSYNC.
1 = GPIO_B state sent to processor over PMSYNC.
28
GPIO_A to PMSYNC Enable (GPIO_A_PMSYNC_EN) — R/W.
0 = GPIO_A (as selected in) pin state not sent to processor over PMSYNC.
1 = GPIO_A state sent to processor over PMSYNC.
27:0 CIR22 Field 1 — R/W. BIOS must program this field to 670060h.