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Intel 6 SERIES CHIPSET - DATASHEET 01-2011 - Page 473

Intel 6 SERIES CHIPSET - DATASHEET 01-2011
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Datasheet 473
LPC Interface Bridge Registers (D31:F0)
13.1.38.4 FVEC3—Feature Vector Register 3
FVECIDX.IDX: 0011b Attribute: RO
Default Value: See Description Size: 32 bit
Power Well: Core
13.1.39 RCBA—Root Complex Base Address Register
(LPC I/F—D31:F0)
Offset Address: F0–F3h Attribute: R/W
Default Value: 00000000h Size: 32 bit
Bit Description
31:14 Reserved
13
Data Center Manageability Interface (DCMI) Capability — RO
0 = Capable
1 = Disabled
12
Node Manager Capability — RO
0 = Capable
1 = Disabled
11:0 Reserved
Bit Description
31:14
Base Address (BA) — R/W. Base Address for the root complex register block decode
range. This address is aligned on a 16-KB boundary.
13:1 Reserved
0
Enable (EN) — R/W. When set, this bit enables the range specified in BA to be claimed
as the Root Complex Register Block.

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