Datasheet 639
SATA Controller Registers (D31:F5)
15.3.2.3 PxSERR—Serial ATA Error Register (D31:F5)
Address Offset: Attribute: R/WC
Default Value: 00000000h Size: 32 bits
SDATA when SINDx.RIDX is 02h.
Bits 26:16 of this register contains diagnostic error information for use by diagnostic
software in validating correct operation or isolating failure modes. Bits 11:0 contain
error information used by host software in determining the appropriate response to the
error condition. If one or more of bits 11:8 of this register are set, the controller will
stop the current transfer.
Bit Description
31:27 Reserved
26
Exchanged (X) — R/WC. When set to 1, this bit indicates that a change in device
presence has been detected since the last time this bit was cleared. This bit shall
always be set to 1 anytime a COMINIT signal is received. This bit is reflected in the
P0IS.PCS bit.
25
Unrecognized FIS Type (F) — R/WC. Indicates that one or more FISs were received
by the Transport layer with good CRC, but had a type field that was not recognized.
24
Transport state transition error (T) — R/WC. Indicates that an error has occurred in
the transition from one state to another within the Transport layer since the last time
this bit was cleared.
23
Transport state transition error (T) — R/WC. Indicates that an error has occurred in
the transition from one state to another within the Transport layer since the last time
this bit was cleared.
22
Handshake (H) — R/WC. Indicates that one or more R_ERR handshake response was
received in response to frame transmission. Such errors may be the result of a CRC
error detected by the recipient, a disparity or 8b/10b decoding error, or other error
condition leading to a negative handshake on a transmitted frame.
21
CRC Error (C) — R/WC. Indicates that one or more CRC errors occurred with the Link
Layer.
20 Disparity Error (D) — R/WC. This field is not used by AHCI.
19
10b to 8b Decode Error (B) — R/WC. Indicates that one or more 10b to 8b decoding
errors occurred.
18
Comm Wake (W) — R/WC. Indicates that a Comm Wake signal was detected by the
Phy.
17 Phy Internal Error (I) — R/WC. Indicates that the Phy detected some internal error.
16
PhyRdy Change (N) — R/WC. When set to 1, this bit indicates that the internal
PhyRdy signal changed state since the last time this bit was cleared. In the PCH, this bit
will be set when PhyRdy changes from a 0 -> 1 or a 1 -> 0. The state of this bit is then
reflected in the PxIS.PRCS interrupt status bit and an interrupt will be generated if
enabled. Software clears this bit by writing a 1 to it.
15:12 Reserved
11
Internal Error (E) — R/WC. The SATA controller failed due to a master or target abort
when attempting to access system memory.
10
Protocol Error (P) — R/WC. A violation of the Serial ATA protocol was detected.
NOTE: The PCH does not set this bit for all protocol violations that may occur on the
SATA link.
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