Intel 6 SERIES CHIPSET - DATASHEET 01-2011 - Page 765

Datasheet 765
PCI Express* Configuration Registers
19.1.15 SSTS—Secondary Status Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7)
Address Offset: 1Eh–1Fh Attribute: R/WC
Default Value: 0000h Size: 16 bits
Bit Description
15
Detected Parity Error (DPE) — R/WC.
0 = No error.
1 = The port received a poisoned TLP.
14
Received System Error (RSE) — R/WC.
0 = No error.
1 = The port received an ERR_FATAL or ERR_NONFATAL message from the device.
13
Received Master Abort (RMA) — R/WC.
0 = Unsupported Request not received.
1 = The port received a completion with “Unsupported Request” status from the device.
12
Received Target Abort (RTA) — R/WC.
0 = Completion Abort not received.
1 = The port received a completion with “Completion Abort” status from the device.
11
Signaled Target Abort (STA) — R/WC.
0 = Completion Abort not sent.
1 = The port generated a completion with “Completion Abort” status to the device.
10:9
Secondary DEVSEL# Timing Status (SDTS): Reserved per PCI Express* Base
Specification.
8
Data Parity Error Detected (DPD) — R/WC.
0 = Conditions below did not occur.
1 = Set when the BCTRL.PERE (D28:FO/F1/F2/F3/F4/F5:3E: bit 0) is set, and either of
the following two conditions occurs:
•Port receives completion marked poisoned.
•Port poisons a write request to the secondary side.
7
Secondary Fast Back to Back Capable (SFBC): Reserved per PCI Express* Base
Specification.
6 Reserved
5 Secondary 66 MHz Capable (SC66): Reserved per PCI Express* Base Specification.
4:0 Reserved