Intel 6 SERIES CHIPSET - DATASHEET 01-2011 - Page 794

PCI Express* Configuration Registers
794 Datasheet
19.1.55 UEM—Uncorrectable Error Mask
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: 108h–10Bh Attribute: R/WO, RO
Default Value: 00000000h Size: 32 bits
When set, the corresponding error in the UES register is masked, and the logged error
will cause no action. When cleared, the corresponding error is enabled.
Bit Description
31:21 Reserved
20
Unsupported Request Error Mask (URE) — R/WO.
0 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5/F6/F7:144) is
enabled.
1 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5/F6/F7:144) is
masked.
19 ECRC Error Mask (EE) — RO. ECRC is not supported.
18
Malformed TLP Mask (MT) — R/WO.
0 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5/F6/F7:144) is
enabled.
1 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5/F6/F7:144) is
masked.
17
Receiver Overflow Mask (RO) — R/WO.
0 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5/F6/F7:144) is
enabled.
1 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5/F6/F7:144) is
masked.
16
Unexpected Completion Mask (UC) — R/WO.
0 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5/F6/F7:144) is
enabled.
1 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5/F6/F7:144) is
masked.
15
Completion Abort Mask (CA) — R/WO.
0 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5/F6/F7:144) is
enabled.
1 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5/F6/F7:144) is
masked.
14
Completion Timeout Mask (CT) — R/WO.
0 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5/F6/F7:144) is
enabled.
1 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5/F6/F7:144) is
masked.
13
Flow Control Protocol Error Mask (FCPE) — RO. Flow Control Protocol Errors not
supported.
12
Poisoned TLP Mask (PT) — R/WO.
0 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5/F6/F7:144) is
enabled.
1 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5/F6/F7:144) is
masked.
11:5 Reserved