Intel 6 SERIES CHIPSET - DATASHEET 01-2011 - Page 798

PCI Express* Configuration Registers
798 Datasheet
19.1.61 PECR2 — PCI Express* Configuration Register 2
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: 320–323h Attribute: R/W
Default Value: 60005007h Size: 32 bits
19.1.62 PEETM — PCI Express* Extended Test Mode Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: 324h–327h Attribute: RO
Default Value: See Description Size: 32 bits
19.1.63 PEC1 — PCI Express* Configuration Register 1
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: 330 Attribute: RO, R/W
Default Value: 14000016h Size: 32 bits
§ §
Bit Description
31:20 Reserved
21 PECR2 Field 1 — R/W. BIOS must set this bit to 1b.
20:0 Reserved
Bit Description
31:3 Reserved
2
Scrambler Bypass Mode (BAU) — R/W.
0 = Normal operation. Scrambler and descrambler are used.
1 = Bypasses the data scrambler in the transmit direction and the data de-scrambler in
the receive direction.
NOTE: This functionality intended for debug/testing only.
NOTE: If bypassing scrambler with the PCH root port 1 in x4 configuration, each PCH
root port must have this bit set.
1:0 Reserved
Bit Description
31:8 Reserved
7:0 PEC1 Field 1 — R/W. BIOS must program this field to 40h.