Intel 6 SERIES CHIPSET - DATASHEET 01-2011 - Page 916

Intel® Management Engine Interface (MEI) Subsystem Registers (D22:F0)
916 Datasheet
23.8.1 IDEPBMCR—IDE Primary Bus Master Command
Register (IDER—D22:F2)
Address Offset: 00h Attribute: RO, R/W
Default Value: 00h Size: 8 bits
This register implements the bus master command register of the primary channel.
This register is programmed by the Host.
23.8.2 IDEPBMDS0R—IDE Primary Bus Master Device
Specific 0 Register (IDER—D22:F2)
Address Offset: 01h Attribute: R/W
Default Value: 00h Size: 8 bits
Bit Description
7:4 Reserved
3
Read Write Command (RWC) — R/W. This bit sets the direction of bus master
transfer.
0 = Reads are performed from system memory
1 = Writes are performed to System Memory.
This bit should not be changed when the bus master function is active.
2:1 Reserved
0
Start/Stop Bus Master (SSBM) — R/W. This bit gates the bus master operation of
IDE function when 0. Writing 1 enables the bus master operation. Bus master
operation can be halted by writing a 0 to this bit. Operation cannot be stopped and
resumed.
This bit is cleared after data transfer is complete as indicated by either the BMIA bit
or the INT bit of the Bus Master status register is set or both are set.
Bit Description
7:0 Device Specific Data0 (DSD0) — R/W. Device Specific