Intel 6 SERIES CHIPSET - DATASHEET 01-2011 - Page 921

Datasheet 921
Intel® Management Engine Interface (MEI) Subsystem Registers (D22:F0)
23.8.15 IDESBMDTPR2—IDE Secondary Bus Master Descriptor
Table Pointer Byte 2 Register (IDER—D22:F2)
Address Offset: 0Eh Attribute: R/W
Default Value: 00h Size: 8 bits
23.8.16 IDESBMDTPR3—IDE Secondary Bus Master Descriptor
Table Pointer Byte 3 Register (IDER—D22:F2)
Address Offset: 0Fh Attribute: R/W
Default Value: 00h Size: 8 bits
Bit Description
7:0
Descriptor Table Pointer Byte 2 (DTPB2) — R/W. This register implements the
Byte 2 (of four bytes) of the descriptor table Pointer (four I/O byte addresses) for bus
master operation of the secondary channel. This register is programmed by the Host.
Bit Description
7:0
Descriptor Table Pointer Byte 3 (DTPB3) — R/W. This register implements the
Byte 3 (of four bytes) of the descriptor table Pointer (four I/O byte addresses) for bus
master operation of the secondary channel. This register is programmed by the Host.