Intel 6 SERIES CHIPSET - DATASHEET 01-2011 - Page 926

Intel® Management Engine Interface (MEI) Subsystem Registers (D22:F0)
926 Datasheet
23.9.10 SVID—Subsystem Vendor ID Register (KT—D22:F3)
Address Offset: 2Ch–2Dh Attribute: R/WO
Default Value: 0000h Size: 16 bits
23.9.11 SID—Subsystem ID Register (KT—D22:F3)
Address Offset: 2Eh–2Fh Attribute: R/WO
Default Value: 8086h Size: 16 bits
23.9.12 CAP—Capabilities Pointer Register (KT—D22:F3)
Address Offset: 34h Attribute: RO
Default Value: C8h Size: 8 bits
This optional register is used to point to a linked list of new capabilities implemented by
the device.
23.9.13 INTR—Interrupt Information Register (KT—D22:F3)
Address Offset: 3C–3Dh Attribute: R/W, RO
Default Value: 0200h Size: 16 bits
Bit Description
15:0
Subsystem Vendor ID (SSVID) — R/WO. Indicates the sub-system vendor
identifier. This field should be programmed by BIOS during boot-up. Once written, this
register becomes Read Only. This field can only be cleared by PLTRST#.
NOTE: Register must be written as a DWord write with SID register.
Bit Description
15:0
Subsystem ID (SSID) — R/WO. Indicates the sub-system identifier. This field should
be programmed by BIOS during boot-up. Once written, this register becomes Read
Only. This field can only be cleared by PLTRST#.
NOTE: Register must be written as a DWord write with SVID register.
Bit Description
7:0
Capability Pointer (CP)— RO. This field indicates that the first capability pointer is
offset C8h (the power management capability).
Bit Description
15:8
Interrupt Pin (IPIN)— RO. A value of 1h/2h/3h/4h indicates that this function
implements legacy interrupt on INTA/INTB/INTC/INTD, respectively
FunctionValueINTx
(3 KT/Serial Port)02hINTB
7:0
Interrupt Line (ILINE)— R/W. The value written in this register tells which input of
the system interrupt controller, the device's interrupt pin is connected to. This value
is used by the OS and the device driver, and has no affect on the hardware.