Datasheet 927
Intel® Management Engine Interface (MEI) Subsystem Registers (D22:F0)
23.9.14 PID—PCI Power Management Capability ID Register
(KT—D22:F3)
Address Offset: C8–C9h Attribute: RO
Default Value: D001h Size: 16 bits
23.9.15 PC—PCI Power Management Capabilities ID Register
(KT—D22:F3)
Address Offset: CA–CBh Attribute: RO
Default Value: 0023h Size: 16 bits
23.9.16 MID—Message Signaled Interrupt Capability ID
Register (KT—D22:F3)
Address Offset: D0–D1h Attribute: RO
Default Value: 0005h Size: 16 bits
Message Signalled Interrupt is a feature that allows the device/function to generate an
interrupt to the host by performing a DWORD memory write to a system specified
address with system specified data. This register is used to identify and configure an
MSI capable device.
Bit Description
15:8 Next Capability (NEXT)— RO. A value of D0h points to the MSI capability.
7:0
Cap ID (CID)— RO. This field indicates that this pointer is a PCI power
management.
Bit Description
15:11 PME Support (PME)— RO.This field indicates no PME# in the PT function.
10:6 Reserved
5
Device Specific Initialization (DSI)— RO. This bit indicates that no device-specific
initialization is required.
4Reserved
3
PME Clock (PMEC)— RO. This bit indicates that PCI clock is not required to generate
PME#
2:0
Version (VS)— RO. This field indicates support for the PCI Power Management
Specification, Revision 1.2.
Bit Description
15:8 Next Pointer (NEXT)— RO. This value indicates this is the last item in the list.
7:0
Capability ID (CID)— RO. This field value of Capabilities ID indicates device is
capable of generating MSI.
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