54
PIN CONFIGURATION
LOGIC SYMBOL (IEEE/IEC)
PIN DESCRIPTION
Pin Number Symbol Function
1, 2 D
sa
, D
sb
Date inputs
3, 4, 5, 6 Q
0
to Q
7
Outputs
10, 11, 12, 13
7 GND Ground(ov)
8 CP Clock input (LOW-to-HIGH, edge-trig-gered)
9 MR Master reset input (active LOW)
14 V
CC
Positive supply voltage
SV00381
LOGIC SYMBOL
FUNCTIONAL DIAGRAM
SV00382 SV00383
SV00384
NOTES 1: C
PD
is used to determine the dynamic power dissipation (P
D
in µW)
P
D
= CPD x V
CC
2
x f
i
+ ∑(C
L
x V
CC
2
x f
O
) where:
f
i
= input frequency in MHz; C
L
= output load capacitance in pF;
f
O
= output frequency in MHz; V
CC
= supply voltage in V;
∑(C
L
x V
CC
2
x f
O
) = sum of the outputs.
2: The condition is V
l
= GND to V
CC
Symbol Parameter Conditions Typical Unit
t
PHL
, t
PLH
Propagation delay C
L
=15pF 12 ns
CP to Q
n
V
CC
=3.3V 12
MR to Q
n
f
max
Maximum clock frequency 78 MH
Z
C
l
Input capacitance 3.5 pF
C
PD
Power dissipation capacitance per gate V
CC
=3.3V 40 pF
Notes 1 and 2
ORDERING INFORMATION
Packages Temperature Range Outside North Amerlca North Amerlca Pkg. Dwg.#
14-Pin Plastic DIL
-40°C to + 125°C 74LV164N 74LV164N SOT27-1
14-Pin Plastic SO
-40°C to + 125°C 74LV164D 74LV164D SOT108-1
14-Pin Plastic SSOP Type II
-40°C to + 125°C 74LV164DB 74LV164DB SOT337-1
14-Pin Plastic TSSOP Type I
-40°C to + 125°C 74LV164PW 74LV164PW DH SOT402-1
74LV164 8-bit SERIAL-IN / PARALLEL-OUT SHIFT REGISTER
FEATURES
–Wide operating voltage: 1.0 to 5.5V
– Optimized for Low Voltage applications: 1.0 to 3.6V
– Accepts TTL input levels between V
CC
=2.7V and V
CC
=3.6V
–Typical V
OLP
(output ground bounce) < 0.8V@V
CC
=3.3V, T
amb
=25°C
–Typical V
OHV
(output V
OH
undershoot) > 2V@V
CC
=3.3V, T
amb
=25°C
– Gated serial data inputs – Asynchronous master reset
– Output capability: standard – I
CC
category: MSl
DESCRIPTION
The 74LV164 is a low-voltage Si-gate CMOS device and is pin and function compatible with the 74HC/HCT164.
The 74LV164 is an 8-bit edge-triggered shift register with serial data entry and an output from each of the
eight stages. Data is entered serially through one of two inputs(D
sa
or D
sb
); either input can be used as an
active HIGH enable for data entry through the other input. Both inputs must be connected together or an
unused input must be tied HIGH.
Data shifts one place to the right on each LOW-to-HIGH transition of the clock (CP) input and enters into Q
0
,
which is the logical AND of the two data inputs (D
sa
, D
sb
) that existed one set-up time prior to the rising clock edge.
A LOW on the master reset (MR) input overrides all other inputs and clears the register asynchronously,
forcing all outputs LOW.
QUICK REFERENCE DATA
GND = OV; T
amb
= 25°C; t
r
=t
f
≤ 2.5ns
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