JVC MX-J570V - Page 54

MX-J570V/MX-J680V
1-54
STTA
SDATA
SCK
BIAS1
BIAS2
BIAS3
RECB
DG
VDD
CE
RECH
SOL-RP
MOTOR
RMUTE
QS'
QS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1.Pin layout
8-STAGE
SHIFT REGISTER
8-BIT
LATHES
3-STATE
OUTPUTS
1
2
3
15
Q1
Q8
10
9
DATA
CLOCK
STROBE
OUTPUT
ENABLE
PARALLEL OUTPUT
Q's
Qs
SERIAL
OUTPUT
2.Block diagram
BU4094BCF (IC303,IC304) : Serial to parallel port extension