Keysight N9320B - Status Register System

Status Registers
Status Register System
28
Status Register System
The hardware status registers are combined to form the instrument
status system. Specific status bits are assigned to monitor various
aspects of the instrument operation and status. See the following
diagram of the status system for information about the bit
assignments and status register interconnections.
Figure 1 Keysight N9320B Status Register System
Event Enable Reg
.
7
6
5
4
3
2
1
0
&
&
&
&
&
&
&
+
0
1
2
3
4
5
6
7
Status Byte Register (*STB?)
Unused
Unused
Error/Event Queue Summary
Questionable Status Summary
Message Available (MAV)
Std. Event Status Sum
Req. Serv. Sum (RQS)
Operation Status Sum
+
0
1
2
3
4
5
6
7
Standard Event Status Register
Oper. Complete
Req. Bus Control
Query Error
Dev. Dep. Error
Execution Error
Command Error
Reserved
Power on
Service Request Enable Register
(*ESE,*ESE?,*ESR?,*OPC)
(*SRE,*SRE?)
Standard OPERation
&
+
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
STATus:QUEStionable:INTegrity
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Setting Limited/Readjusted
Always Zero
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
+
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Always Zero
Reserved
Reserved
Reserved
Reserved
MEASuring
Reserved
Reserved
Reserved