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Kirisun TR850 - Radio Overview; Front and Rear Panel Components

Kirisun TR850
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TR850 Service Manual
3.1.1. Tx Circuit
Figure 3-1 Transmitter Circuit
X100
MODE1
SDATA
TXPLLCS
SCLK
TXLD
MODEIN
Q2002
IC100 SKY72310
IC306
U402
TOTXPA
MODE2
TXVCOSELECT
TXVCO1+TXVCO2
Q105
Q106
TXENABLE
Transmitter circuit includes three parts:
Two Point Modulation Circuit
The RF center frequency calibration from the baseband and the low frequency part of 4FSK signal will
be processed with addition algorithm, then sent to the DAC to get MODE1 signal. The MODE1 directly
enters the reference clock X100, which is used for center frequency control and low frequency modulation.
The MODE2 signal, which passes the two-level low pass filter which is composed of IC301s for DAC
sampling interference filter, will be sent into VCO for high frequency part modulation.
Transmitter Frequency Generation Unit Circuit
The transmitter PLL includes two VCOs,one PLL(IC100) IC SKY72310 and reference clock X100. The
transmitting frequencies of the two VCOs controlled by the TXVCOSELECT signal are 400~435MHz and
435~470MHz respectively.(VHF is 136~155MHz and 155~174MHz)
a. Working Principle of Voltage Controlled Oscillator
The Tx Module employs two VCOs which cover the band of 400~435MHz and 435~470MHz (VHF is
136~155MHz and 155~174MHz). The switch of VCO is controlled by the TXVCOSELECT signal. VCO
employs three point capacitance oscillation circuit. The VCO that covers the band of 400~435MHz (VHF is
136~155MHz) is composed of D106~D109L119Q106 and some other components, while the VCO
covers the band of 435~470MHz (VHF is 155~174MHz) is composed of D101~D104L107Q105 and
some other components.
b. Working Principle of Frequency Generation Unit
The 12.8 MHz reference clock (X100) output signal which is controlled by MODE1 signal will enter the
reference input port of PLL IC (IC100 SKY72310), then according to the configuration of register, it will be
divided to get 3.2MHz reference frequency, and the frequency will be compared in phase difference with
the signal generated by the frequency division which is resulted from the VCOs enter into the input port of
PLL chip. The PLL (IC100 SKY72310) PD pin will output the positive or negative pulse current which is in
output pulse width, is directly proportional to the aforementioned signal phase difference. When the pulse
4

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