The two address busses are tri-state
multiplex~~
onto a
common Soundfile Address bus (SFADDR). The buffer enables are
tied to
CPSFIPI
·and
CGSFIP/. When arbitration has occurred, these
signals indicate access to soundfile memory, and
50 ns. is allowed
for the signals
to
settle
on
the SFADQR
b.us.
On
the next cycle RASI
will always go low, which signifies that the addresses are valid, and
the access time of the memory begins (usually 250 to 350 ns.).
During the
RASI state, we require that the memory control signals
such as read/write and
SOUND, the mode control, become valid. This
allows the data paths
to
be
set
up
in
the appropriate way, as well
as
the special circuitry required to generate the SOUND samples.
Depending
on
the memory type (shown
in
figure 3.5) and the setting
of the
DTACK jumper, this may also generate DTACKI to the
requesting device. The next cycle,
CASI
is
generated only if the
RAM
was accessed. There are actually 4
CASI
signals, corresponding
to
UDS/, LDS/, SOUND*UDS/, and SOUND*LDSI (CASH/,
CASU,
SCASHI
and
SCASU).
The main soundfile data path (SFDATA),
is
used for both sound
and data. The
CPU selects the mode it wishes to access soundfile
memory by writing to two locations
in
the CGP address while
RDSOUND changes back into data mode. Both of these accesses have
no
wait stages. When the
CPU
accesses sound, each sample appears
to
occupy a single byte (this
so
that the soundfile can have uniform
addressing, and word transfers can occur
in
one cycle). This means
that the
68000 must pre-store the 2 LSBs of the sound
in
a special
latch (called, not surprisingly, the Sound Latch) before doing a write
to
sound memory, and this is accomplished whenever WRSOUND
occurs. The reading of soundfiles is done by writing WRSOUND,
performing a soundfile access, and then extracting the 2 LSB's
by
reading
RDSOUND.
The 12 channels operate independently in all of the above
tasks, and are time-multiplexed using high-speed (10MHz.) dedicated
logic. Before a channel may
be
enabled, the appropriate parameters
must be loaded by the main
CPU
into the CGP Local Memory.
In
addition, the individual channel must
be
set up
to
generate the
appropriate amplitude, Sampling clock and Anti-Alias clock rate.
Kurzwell 250 Service Manual, Chapter 3
3-
1 7
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