Kurzweil K250 - Page 56

In State 5, the CGP memory is addressed by appending the
channel number
(CHCNT), and the FIFO read pointer to fetch the
appropriate sound sample, and
latch it into a buffer for transfer to
the
Channel board. Next, we increment the FIFO read pointer, and
compare it
to th~ FIFO write pointer. If they are equal then the new
FIFO full is asserted, and the new CSW is writtefn over the old one.
If a DMA cycle is required, the sequence is as follows:
1. Read and latch the low 16 bits of the DMA address.
2. Read and latch the high 8 bits of the DMA address. Also
assert CGP address strobe (CGAS).
3. Perform a Channel Read, if required (identical to State 5).
4. Read,
latch and compare the programmed last address
(LADDR) with the current
DMA address
5. Rewrite the CSW, incrementing the FIFO write pointer, the
FIFO read pointer (if necessary), and updating FIFOFUL.
6. Write the new sound sample into the CGP at the address
pointed to by the
FIFO write pointer.
7. Write the new DMA address for the channel
(old one +1) over
the
old one.
In this way, the CGP attempts to keep all of the active FIFO's
full,
while guaranteeing one-poll service of channel requests.
The other interface requirement is that of the Last Access
(LAST), which performs the following functions;
1.
Inverts the Toggle bit of the CSW, which points to the
current active span parameters.
2. If there is no interrupt pending, the current channel number
(CHCNT) and a single bit (UPDATE) are latched into a buffer
for examination by a
CPU. The format of the Vector byte is:
VECTOR: I 0 0 I 0 C B A I u I 0 I
CHCNT UPDA
Kurzwell 250 Service Manual, Chapter 3
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