Refer now to the diagram labeled Handshake Diagram for a
Single Channel (figure 3.11).
As
mentioned earlier, the CGP can
'\
deliver samples generally much more quickly than the Channel board
can take them.
So the function of the interface circuitry on the
Channel board is to throttle the
delivery of
the~
samples to each of
the channels.
It
effectively does this throttling through the 12
signals labeled FSAMP.
Imagine for a moment that the K250 is a 1
channel instrument while looking at this diagram. The signal labeled
LDDAC stands for Load
DAC
Not and is the signal which eventually
causes the signal DAC for this channel
on
the Channel board to be
loaded with a sound sample.
Once the CGP has been told by the
CPU
to start playing out a particular sound were it not for the throttling
effect from the Channel board, the
CGP would just spit out samples
in
rapid fire succession to the Channel
so
the LDDAC signals would
be happening
in
rapid succession.
I
/
Imagine for a moment that the output of the box called 1-bit
register
is
always high. So that the cross coupled gate flip-flop
simply flip flops back and forth
in
response to the LDDAC and the
FSAMP
signal. The output of this cross coupled gate flip-flop is
called CHRDRQ which stands for channel read request. It is this
signal CHRDRQ which signals the
CGP
that the channel is ready for a
new sample. Whenever this line goes low the
CGP will then begin
the process of loading a new sample into the
channel.
But this signal CHRDRQ will only go low
in
response to the
FSAMP input going
low, but this is precisely the time when you want
the sample to be delivered. That
is,
in
synchronization with the
FSAMP signal.
Once that sample has been loaded into the
DAC
by the
LDDAC
pulse, then this same signal LDDAC sets the cross coupled
gate flip-flop to the other state and causes CHRDRQ to go high. When
the
CGP
sees the signal CHRDRQ go high, it will deliver
no
further
samples until CHRDRQ goes low again, which will happen only when
the next FSAMP pulse goes low.
It is
in
this way that the sampling
clock or FSAMP throttles the loading of the sampling information
into
channel. This all assumes that the output of the 1-bit register
is always high. This would be the case if the channel is turned on.
If that channel is not turned on, that is, not intended to play any
sound, then the
outP,ut
of this register will be low by forcing the
signal CHRDRQ to always reside iligh, which then causes the CGP
to
not load samples into that channel.
Kurzwell 250 Service Manual, Chapter 3
3-
29
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