LabJack U12 - Page 57

Baud rate and timeout period must be set by writing to the proper RAM locations. Timeout in milliseconds is about 100*tomult.
Command
Byte #
Description
0
Data Byte 3
1
Data Byte 2
2
Data Byte 1
3
Data Byte 0
4
Bits 7-4: XXXX
Bit 3: 1 bit delay between each tx byte
Bit 2: Timeout active?
Bit 1: Set transmit enable?
Bit 0: port B?
5
011XXXX1 (Asynch)
6
Number of bytes to write (0-18)
7
Number of bytes to read (0-18)
Response
Byte #
Description
0
Data Byte 3
1
Data Byte 2
2
Data Byte 1
3
Data Byte 0
4
Bits 7-6: XX
Bit 5: Timeout Error Flag
Bit 4: STRT Error Flag
Bit 3: FRM Error Flag
Bit 2: RXTris Error Flag
Bit 1: TETris Error Flag
Bit 0: TXTris Error Flag
5
011XXXX1
6
Number of bytes to write (0-18)
7
Number of bytes to read (0-18)
LabJackPython Example
>>> import u12
>>> d = u12.U12()
open called
Writing: [0x0, 0x0, 0x0, 0x0, 0x0, 0x57, 0x0, 0x0]
Received: [0x57, 0x0, 0x0, 0x0, 0xff, 0xff, 0x0, 0x0]
>>> # Set the full and half A,B,C to 9600
>>> d.rawWriteRAM([0, 1, 1, 200], 0x073)
Writing: [0xc8, 0x1, 0x1, 0x0, 0x0, 0x51, 0x0, 0x73]
Received: [0x51, 0xc8, 0x1, 0x1, 0x0, 0x0, 0x0, 0x73]
{'DataByte3': 200, 'DataByte2': 1, 'DataByte1': 1, 'DataByte0': 0}
>>> d.rawWriteRAM([5, 1, 2, 48], 0x076)
Writing: [0x30, 0x2, 0x1, 0x5, 0x0, 0x51, 0x0, 0x76]
Received: [0x51, 0x30, 0x2, 0x1, 0x5, 0x0, 0x0, 0x76]
{'DataByte3': 48, 'DataByte2': 2, 'DataByte1': 1, 'DataByte0': 5}
>>> d.rawAsynch([1, 2, 3, 4], NumberOfBytesToWrite = 4, NumberOfBytesToRead = 4)
Writing: [0x4, 0x3, 0x2, 0x1, 0x0, 0x61, 0x4, 0x4]
Received: [0x4, 0x3, 0x2, 0x1, 0x1, 0x61, 0x4, 0x4]
{
'DataByte3': 4, 'DataByte2': 3, 'DataByte1': 2, 'DataByte0': 1,
'ErrorFlags':
<BitField object: [ Timeout Error Flag = 0 (0),
STRT Error Flag = 0 (0),
FRM Error Flag = 0 (0),
RXTris Error Flag = 0 (0),
TETris Error Flag = 0 (0),
TXTris Error Flag = 1 (1) ] >
}
5.14 - SPI
Sends and receives data synchronously (SPI). First four bytes sent/received are passed in this call, and copied to the first 4 bytes
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