EasyManua.ls Logo

Lattice Semiconductor ECP5 - Card #1 Expansion Connector Pinout

Default Icon
41 pages
Print Icon
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Loading...
31
ECP5 PCI Express Board User’s Guide
5
5
4
4
3
3
2
2
1
1
D
D
C
C
B
B
A A
Use 85-ohm traces for
differential pairs.
The P and N traces shall be
<20mil matched in length
B side = Primary
Component Side(TOP)
A side = Secondary
Component
Side(BOTTOM)
54MHz OSC Clk
Mipi Rx
1 Clock Pair
4 Data Pairs
SPI Bus
SERDES
Diff Rx/Tx
2x1 Rx/Tx Clock Pair
2x4 Rx/Tx Data Pairs
JTAG
LVCMOS
40 IOs
#1 Proto
To avoid damage do not
plug CN3 into PCIe slots
#1
Card Detect
LVCMOS
JTAG
Diff Rx/Tx
I2C Bus
SERDES
SPI Bus
Mipi Rx
12_0V
2_5V 2_5V
12_0V
Lvds1Tx3p [Pg21]
Lvds1Tx3n [Pg21]
Lvds1Tx0p [Pg21]
Lvds1Tx0n [Pg21]
Lvds1TxCp [Pg21]
Lvds1TxB3p [Pg21]
Lvds1TxB3n [Pg21]
Lvds1TxB0p [Pg21]
Lvds1TxB0n [Pg21]
Lvds1TxBCp [Pg21]
Lvds1TxBCn [Pg21]
Lvds1Rx4p [Pg23]
Lvds1Rx4n [Pg23]
Lvds1Rx2p [Pg23]
Lvds1Rx2n [Pg23]
Lvds1Rx1p [Pg23]
Lvds1Rx1n [Pg23]
Lvds1RxB4p [Pg23]
Lvds1RxB4n [Pg23]
Lvds1RxB2p [Pg23]
Lvds1RxB2n [Pg23]
Lvds1RxB1p [Pg23]
Lvds1RxB1n [Pg23]
Lvcmos1_0 [Pg13,19]
Lvcmos1C_1 [Pg13,19]
Lvcmos1_4 [Pg13,19]
Lvcmos1_5 [Pg13,19]
Lvcmos1_8 [Pg13,19]
Lvcmos1_9 [Pg13,19]
Lvcmos1_12 [Pg13,19]
Lvcmos1_16 [Pg13,19]
Lvcmos1_17 [Pg13,19]
Lvcmos1_20 [Pg13,19]
Lvcmos1_21 [Pg13,19]
Lvcmos1_24 [Pg13,19]
Lvcmos1_25 [Pg13,19]
Lvcmos1_28 [Pg13,19]
Lvcmos1_29 [Pg13,19]
Lvcmos1_32 [Pg13,19]
Lvcmos1_33 [Pg13,19]
Lvcmos1_36 [Pg13,19]
Lvcmos1_37 [Pg13,19]
Lvcmos1_13 [Pg13,19]
SPI_MISO [Pg14,19]
SPI_SCLK [Pg14,19]
Card1_TCK [Pg9]
Card1_TDI [Pg9]
Lvds1TxCn [Pg21]
MipiRx2n [Pg20]
MipiRx2p [Pg20]
MipiRxCn [Pg20]
MipiRxCp [Pg20]
MipiRx1n [Pg20]
MipiRx1p [Pg20]
CLK54a [Pg12]
Lvcmos1_0[Pg13,19]
Lvcmos1C_1[Pg13,19]
Lvcmos1_4[Pg13,19]
Lvcmos1_5[Pg13,19]
Lvcmos1_8[Pg13,19]
Lvcmos1_9[Pg13,19]
Lvcmos1_12[Pg13,19]
Lvcmos1_16[Pg13,19]
Lvcmos1_17[Pg13,19]
Lvcmos1_20[Pg13,19]
Lvcmos1_21[Pg13,19]
Lvcmos1_24[Pg13,19]
Lvcmos1_25[Pg13,19]
Lvcmos1_28[Pg13,19]
Lvcmos1_29[Pg13,19]
Lvcmos1_32[Pg13,19]
Lvcmos1_33[Pg13,19]
Lvcmos1_36[Pg13,19]
Lvcmos1_37
[Pg13,19]
Lvcmos1_13[Pg13,19]
Lvcmos1_2 [Pg13,19]
Lvcmos1_3 [Pg13,19]
Lvcmos1_6 [Pg13,19]
Lvcmos1_7 [Pg13,19]
Lvcmos1_10 [Pg13,19]
Lvcmos1_11 [Pg13,19]
Lvcmos1_14 [Pg13,19]
Lvcmos1_15 [Pg13,19]
Lvcmos1_18 [Pg13,19]
Lvcmos1_19 [Pg13,19]
Lvcmos1_22 [Pg13,19]
Lvcmos1_23 [Pg13,19]
Lvcmos1_26 [Pg13,19]
Lvcmos1_27 [Pg13,19]
Lvcmos1_30 [Pg13,19]
Lvcmos1_31 [Pg13,19]
Lvcmos1_34 [Pg13,19]
Lvcmos1_35 [Pg13,19]
Lvcmos1_38 [Pg13,19]
Lvcmos1_39 [Pg13,19]
Card1_TDO[Pg9]
Card1_TMS[Pg9]
MipiRx0n[Pg20]
MipiRx0p[Pg20]
Lvds1Tx2p[Pg21]
Lvds1Tx2n[Pg21]
Lvds1Tx1p[Pg21]
Lvds1Tx1n[Pg21]
Lvds1TxB2p[Pg21]
Lvds1TxB2n[Pg21]
Lvds1TxB1p[Pg21]
Lvds1TxB1n[Pg21]
Lvds1Rx3p[Pg23]
Lvds1Rx3n[Pg23]
Lvds1Rx0p[Pg23]
Lvds1Rx0n[Pg23]
Lvds1RxCp
[Pg23]
Lvds1RxCn[Pg23]
Lvds1RxB3p[Pg23]
Lvds1RxB3n[Pg23]
Lvds1RxB0p[Pg23]
Lvds1RxB0n[Pg23]
Lvds1RxBCp[Pg23]
Lvds1RxBCn[Pg23]
Lvcmos1_2[Pg13,19]
Lvcmos1_3[Pg13,19]
Lvcmos1_6[Pg13,19]
Lvcmos1_7[Pg13,19]
Lvcmos1_10[Pg13,19]
Lvcmos1_11[Pg13,19]
Lvcmos1_14[Pg13,19]
Lvcmos1_15[Pg13,19]
Lvcmos1_18[Pg13,19]
Lvcmos1_19[Pg13,19]
Lvcmos1_22[Pg13,19]
Lvcmos1_23[Pg13,19]
Lvcmos1_26[Pg13,19]
Lvcmos1_27[Pg13,19]
Lvcmos1_30
[Pg13,19]
Lvcmos1_31[Pg13,19]
Lvcmos1_34
[Pg13,19]
Lvcmos1_35[Pg13,19]
Lvcmos1_38[Pg13,19]
Lvcmos1_39[Pg13,19]
c1_x4_PCIE_CLKN
[Pg15]
c1_PCSC_HDOUTP0 [Pg15]
c1_PCSC_HDOUTN0 [Pg15]
c1_x4_PETn0 [Pg15]
c1_x4_PETp0 [Pg15]
MipiRx3n[Pg20]
MipiRx3p[Pg20]
SPI_MOSI
[Pg14,19]
SPI_SN_C1[Pg19]
c1_x4_PETn1[Pg15]
c1_x4_PETp1[Pg15]
I2C1_SDA[Pg19]
c1_PCSC_HDOUTP1[Pg15]
c1_PCSC_HDOUTN1[Pg15]
I2C1_SCL[Pg19]
c1_x4_PCIE_CLKP[Pg15]
Date:
Size
Schematic Rev
ofSheet
Title
Lattice Semiconductor Applications
Email: techsupport@Latticesemi.com
Board Rev
Project
Nov, 2012
B
B
2813
B
Date:
Size
Schematic Rev
ofSheet
Title
Lattice Semiconductor Applications
Email: techsupport@Latticesemi.com
Board Rev
Project
Nov, 2012
B
B
2813
B
Date:
Size
Schematic Rev
ofSheet
Title
Lattice Semiconductor Applications
Email: techsupport@Latticesemi.com
Board Rev
Project
Nov, 2012
B
B
2813
Card #1
B
J1
HEADER 22X2
DNI
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
CN1
I2C1_SDA
A1
GND_A3
A3
MipiRx3n
A4
I2C1_SCL
A2
MipiRx3p
A5
GND_A6
A6
MIPI RX N_A7
A7
MIPI RX P_A8
A8
GND_A9
A9
SPI_MOSI
A10
SPI_SN_C1
A11
c1_x4_PETp1
A12
c1_x4_PETn1
A13
GND_A14
A14
c1_x4_PCIE_CLKN
A15
c1_x4_PCIE_CLKP
A16
c1_PCSC_HDOUTP1
A17
DIFF TXN_A19
A19
DIFF TXP_A20
A20
+12V_A21
A21
DIFF RXN_A22
A22
DIFF RXP_A23
A23
DIFF TXN_A24
A24
DIFF TXP_A25
A25
GND_A26
A26
DIFF RXN_A27
A27
DIFF RXP_A28
A28
GND_A29
A29
DIFF TXN_A30
A30
DIFF TXP_A31
A31
GND_A32
A32
c1_PCSC_HDOUTN1
A18
DIFF RXN_A33
A33
DIFF RXP_A34
A34
DIFF TXN_A35
A35
DIFF TXP_A36
A36
GND_A37
A37
DIFF RXN_A38
A38
DIFF RXP_A39
A39
DIFF TXN_A40
A40
DIFF TXP_A41
A41
GND_A45
A45
+12V_A42
A42
DIFF RXN_A43
A43
DIFF RXP_A44
A44
DIFF TXN_A46
A46
DIFF TXP_A47
A47
DIFF RXN_A48
A48
DIFF RXP_A49
A49
TDO
A50
TMS
A51
GND_A52
A52
LVCMOS_A53
A53
LVCMOS_A54
A54
+12V_A55
A55
LVCMOS_A56
A56
LVCMOS_A57
A57
LVCMOS_A59
A59
LVCMOS_A60
A60
LVCMOS_A62
A62
LVCMOS_A63
A63
LVCMOS_A65
A65
LVCMOS_A66
A66
LVCMOS_A68
A68
LVCMOS_A69
A69
LVCMOS_A71
A71
LVCMOS_A72
A72
LVCMOS_A74
A74
LVCMOS_A75
A75
GND_A58
A58
+12V_A61
A61
GND_A64
A64
+12V_A67
A67
GND_A70
A70
GND_A73
A73
GND_A76
A76
LVCMOS_A77
A77
LVCMOS_A78
A78
LVCMOS_A80
A80
LVCMOS_A81
A81
GND_A79
A79
SENSE
A82
MIPI RX P_B2
B2
GND_B3
B3
GND_B7
B7
MIPI RX N_B5
B5
MIPI RX P_B6
B6
MISO
B11
SCLK
B12
PM_WRCLK
B13
PM_RDAT
B14
GND_B15
B15
PM_8MHZ
B16
PM_I2C_SCL
B17
GND_B18
B18
DIFF RXN_B19
B19
DIFF RXP_B20
B20
+12V_B21
B21
DIFF TXN_B22
B22
DIFF TXP_B23
B23
DIFF RXN_B24
B24
DIFF RXP_B25
B25
GND_B26
B26
DIFF TXN_B27
B27
DIFF TXP_B28
B28
GND_B29
B29
DIFF RXN_B30
B30
DIFF RXP_B31
B31
GND_B32
B32
DIFF TXN_B33
B33
DIFF TXP_B34
B34
DIFF RXN_B35
B35
DIFF RXP_B36
B36
GND_B37
B37
DIFF TXN_B38
B38
DIFF TXP_B39
B39
DIFF RXN_B40
B40
DIFF RXP_B41
B41
+12V_B42
B42
DIFF TXN_B43
B43
DIFF TXP_B44
B44
GND_B45
B45
DIFF RXN_B46
B46
DIFF RXP_B47
B47
DIFF TXN_B48
B48
DIFF TXP_B49
B49
TCK
B50
TDI
B51
LVCMOS_B52
B52
LVCMOS_B53
B53
+12V_B54
B54
LVCMOS_B55
B55
LVCMOS_B56
B56
GND_B57
B57
LVCMOS_B58
B58
LVCMOS_B59
B59
+12V_B60
B60
LVCMOS_B61
B61
LVCMOS_B62
B62
GND_B63
B63
LVCMOS_B64
B64
LVCMOS_B65
B65
+12V_B66
B66
LVCMOS_B67
B67
LVCMOS_B68
B68
GND_B69
B69
LVCMOS_B70
B70
LVCMOS_B71
B71
GND_B72
B72
LVCMOS_B73
B73
LVCMOS_B74
B74
GND_B75
B75
LVCMOS_B76
B76
LVCMOS_B77
B77
GND_B78
B78
LVCMOS_B79
B79
LVCMOS_B80
B80
GND_B81
B81
MIPI RX N_B1
B1
+12V_B4
B4
+12V_B8
B8
MIPI RX N_B9
B9
MIPI RX P_B10
B10
CLK
B82
PCI Express Board

Other manuals for Lattice Semiconductor ECP5

Related product manuals