5
5
4
4
3
3
2
2
1
1
D
D
C
C
B
B
A A
Place subLVDS Termination Resistors as close as possible to FPGA (U1)
subLVDS Termination Not Installed (TN1210)
Lvds2Tx3p [Pg14]
Lvds2Tx3n [Pg14]
Lvds2Tx2p [Pg14]
Lvds2Tx2n [Pg14]
Lvds2Tx1p [Pg14]
Lvds2Tx1n [Pg14]
Lvds2Tx0p [Pg14]
Lvds2Tx0n [Pg14]
Lvds2TxCp [Pg14]
Lvds2TxCn [Pg14]
Lvds2TxB3p [Pg14]
Lvds2TxB3n [Pg14]
Lvds2TxB2p [Pg14]
Lvds2TxB2n [Pg14]
Lvds2TxB1p [Pg14]
Lvds2TxB1n [Pg14]
Lvds2TxB0p [Pg14]
Lvds2TxB0n [Pg14]
Lvds2TxBCp [Pg14]
Lvds2TxBCn [Pg14]
tLvds2Tx3p[Pg20]
tLvds2Tx3n[Pg20]
tLvds2Tx0p[Pg20]
tLvds2Tx0n
[Pg20]
tLvds2TxCp[Pg20]
tLvds2TxCn
[Pg20]
tLvds2TxB3p[Pg20]
tLvds2TxB3n[Pg20]
tLvds2TxB0p[Pg20]
tLvds2TxB0n[Pg20]
tLvds2TxBCp[Pg20]
tLvds2TxBCn
[Pg20]
tLvds2Tx2p
[Pg20]
tLvds2Tx2n
[Pg20]
tLvds2Tx1p[Pg20]
tLvds2Tx1n
[Pg20]
tLvds2TxB2p[Pg20]
tLvds2TxB2n
[Pg20]
tLvds2TxB1p[Pg20]
tLvds2TxB1n[Pg20]
Date:
Size
Schematic Rev
ofSheet
Title
Lattice Semiconductor Applications
Email: techsupport@Latticesemi.com
Board Rev
Project
Nov, 2012
B
B
2822
ECP5 Bank 2 - 3 #2 Termination
B
Date:
Size
Schematic Rev
ofSheet
Title
Lattice Semiconductor Applications
Email: techsupport@Latticesemi.com
Board Rev
Project
Nov, 2012
B
B
2822
ECP5 Bank 2 - 3 #2 Termination
B
Date:
Size
Schematic Rev
ofSheet
Title
Lattice Semiconductor Applications
Email: techsupport@Latticesemi.com
Board Rev
Project
Nov, 2012
B
B
2822
ECP5 Bank 2 - 3 #2 Termination
B
R105
0
DNI
R0402
R122
0
R0402
R302
0
DNI
R0402
R371
0
DNI
R0402
R138
0
R0402
R101
0
R0402
R119
0
DNI
R0402
R341
0
R0402
R343
0
DNI
R0402
R107
0
R0402
R316
0
R0402
R131
0
R0402
R130
0
DNI
R0402
R345
0
R0402
R98
0
DNI
R0402
R352
0
R0402
R301
0
R0402
R320
0
R0402
R136
0
DNI
R0402
R95
0
R0402
R372
0
R0402
R349
0
R0402
R128
0
R0402
R318
0
DNI
R0402
R117
0
R0402
R350
0
DNI
R0402
R304
0
R0402
R99
0
R0402
R356
0
R0402
R135
0
R0402
PCI Express Board