Lexicon
6-3
The S/PDIF OUT is generated by the Lexichip3 (sheet 3) and buffered by two gate sections of U3
(74HC132). The voltage divider formed by R13-R15 develops an open-circuit voltage at J5 of 1Vp-p, ac-
coupled by C8 and C9. Output impedance is about 75, which produces the standard 500mVp-p S/PDIF
signal when connected to a 75 terminated load. The S/PDIF OUT is gated with RESET/ to mute the digital
output.
S/PDIF IN connected to J5 is terminated in 75 by R18, ac-coupled by C13, and amplified by U4
(74HCU04). Current limiting resistor R19 and clamping diode D3 provide input protection. The amplified
signal is demodulated by digital audio receiver CS8412 (U14), which delivers a serial stream in I2S format
to the Lexichip3. The signals C0/, CA, CB, CC, CD, CE and ERF allow software to determine the lock,
error status, and sample rate detected by U14. CK_6MHZ provides a reference clock used by U14 to
determine incoming sample rate.
For information on CS8412 http://www.cirrus.com/products/overviews
Product data sheet (PDF) http://www.cirrus.com/ftp/pubs
Sheet 6 (DISPLAY DRIVER)
This sheet shows the footswitch jack, LCD connection, LCD contrast, led driver, SW #1 and SW#2
connections and their associated circuits.
The tip and ring of the footswitch ¼” phone jack (J4) connect to FOOT_TAP/ and FOOT_BYPASS/,
respectively, through current-limiting resistors R11 and R12. Capacitors C5 and C6 filter out RFI. D10 and
D11 help protect from over voltage or static discharge. Pull-up resistors R100 and R101 default the non-
active switch state to logic high. FOOT_TAP/ and FOOT_BYPASS/ are fed to 74HC541 (U19), which allows
software to determine the footswitch state.
Signals ENCA and ENCB are from the two-phase incremental rotary encoder on the SW1 board. The
encoder bits are pulled-up by R86 and R87 and filtered by R85, R88, C102 and C103. Software determines
the state of the encoder by reading U19.
Connector (J19) is the interface to the front-panel LCD module. R102-112 are series damping resistors for
the LCD address, control and data lines. 10K-potentiometer (R2) adjusts the LCD contrast. The front-panel
LED’s on the SW#1 and SW#2 boards are controlled by software via U18 (74AC273) and associated
current-limiting resistors.
For information on LCD (PDF) ftp://wfp62508.w1.com/s150gs32.pdf.
Sheet 7 (POWER SUPPLY)
This sheet shows the power supply, reset generator and their associated circuits.
The Reset generator is formed by two sections of U3 (74HC132), along with C11 (22uF) and R16 (1K).
RESET/ is held low during initialization, immediately after power is applied.
Main power is applied to IEC connector (J1). The MPX500 incorporates a switching power supply module,
which accepts main voltages from 90-240V AC. The power switch on front panel is in series with the main
input to the power supply module. The supply delivers +/-15VDC and +5VDC, which is conditioned by
capacitors, resistor and chokes shown.
Additional Sheets 1 each (SW#1, SW#2)
SW#1 incorporates (4) LED’s, (4) switches, and encoder SW5, which connect to the MAIN board via J18.
SW5 is a 24-position rotary encoder, which includes a push-action switch, used to access the bank function
in system.
SW#2 incorporates (2) LED’s and (2) switches, wired to the MAIN board via J20.
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