LG 32LG500H - Page 23

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BLOCK DIAGRAM
LGE Internal Use OnlyCopyright LG Electronics. Inc. All right reserved.
Only for training and service purposes
1. Vide(After)
DIGIT_B_D[0-23]
H,V_SYNC_DIGIT
DE,CLK_DIGIT
TMDS_0 TMDS_1 DDC_I2C_0,1
ATSC/NTSC
Tuner
R,G,B
VGA_H,V SYNC
CABLE_DET
COMPONENT (Y,Pb,Pr)
REAR CVBS SIDE_CVBS S_VIDEO Y,C(rear/side)
TUNER_CVBS
I2S
D2A
INV_BR
DIGITAL_IN[24Bit] DE,CLK_IN DIGITAL_H,V_SYNC ANALOG_IN
ANALOG_H,V_SYNC ANALOG_IN
CABLE_DET COMPONENT_SEL
ANALOG_IN
ANALOG_IN ANALOG_IN ANALOG_IN ANALOG IN
INV_BRI
DISPLAY_EN
AI_ON_OFF/OD SEL_1
LVDS_DATA
LVDS_DATA
DISPLAY_EN
INV_CTL
UART1UART1
LVDS
Connector
For LCD
POWER
HDMI
SiI9023
ANT./Cable
Pro:Idiom
BCM7411
CPLD
12_to_20
DIGITAL_IN[24Bit] DE,CLK_IN DIGITAL_H,V_SYNC
SERIAL_TS
DIGIT_A_D[0-20]
H,V_SYNC_DIGIT
DE,CLK_DIGIT
Cortez-A.
UART0UART0
CPLD
20 BIT
16 BIT
AFAGC_D2A,IFAGC_D2A
IF_P,IF_N
VSB
BLOCK